arm/mach-iop32x/adma.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * platform device definitions for the iop3xx dma/xor engines
0004  * Copyright © 2006, Intel Corporation.
0005  */
0006 #include <linux/platform_device.h>
0007 #include <linux/dma-mapping.h>
0008 #include <linux/platform_data/dma-iop32x.h>
0009
0010 #include "iop3xx.h"
0011 #include "irqs.h"
0012
0013 #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
0014 #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
0015 #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
0016
0017 #define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
0018 #define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
0019 #define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
0020
0021 #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
0022 #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
0023 #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
0024
0025 /* AAU and DMA Channels */
0026 static struct resource iop3xx_dma_0_resources[] = {
0027     [0] = {
0028         .start = IOP3XX_DMA_PHYS_BASE(0),
0029         .end = IOP3XX_DMA_UPPER_PA(0),
0030         .flags = IORESOURCE_MEM,
0031     },
0032     [1] = {
0033         .start = IRQ_DMA0_EOT,
0034         .end = IRQ_DMA0_EOT,
0035         .flags = IORESOURCE_IRQ
0036     },
0037     [2] = {
0038         .start = IRQ_DMA0_EOC,
0039         .end = IRQ_DMA0_EOC,
0040         .flags = IORESOURCE_IRQ
0041     },
0042     [3] = {
0043         .start = IRQ_DMA0_ERR,
0044         .end = IRQ_DMA0_ERR,
0045         .flags = IORESOURCE_IRQ
0046     }
0047 };
0048
0049 static struct resource iop3xx_dma_1_resources[] = {
0050     [0] = {
0051         .start = IOP3XX_DMA_PHYS_BASE(1),
0052         .end = IOP3XX_DMA_UPPER_PA(1),
0053         .flags = IORESOURCE_MEM,
0054     },
0055     [1] = {
0056         .start = IRQ_DMA1_EOT,
0057         .end = IRQ_DMA1_EOT,
0058         .flags = IORESOURCE_IRQ
0059     },
0060     [2] = {
0061         .start = IRQ_DMA1_EOC,
0062         .end = IRQ_DMA1_EOC,
0063         .flags = IORESOURCE_IRQ
0064     },
0065     [3] = {
0066         .start = IRQ_DMA1_ERR,
0067         .end = IRQ_DMA1_ERR,
0068         .flags = IORESOURCE_IRQ
0069     }
0070 };
0071
0072
0073 static struct resource iop3xx_aau_resources[] = {
0074     [0] = {
0075         .start = IOP3XX_AAU_PHYS_BASE,
0076         .end = IOP3XX_AAU_UPPER_PA,
0077         .flags = IORESOURCE_MEM,
0078     },
0079     [1] = {
0080         .start = IRQ_AA_EOT,
0081         .end = IRQ_AA_EOT,
0082         .flags = IORESOURCE_IRQ
0083     },
0084     [2] = {
0085         .start = IRQ_AA_EOC,
0086         .end = IRQ_AA_EOC,
0087         .flags = IORESOURCE_IRQ
0088     },
0089     [3] = {
0090         .start = IRQ_AA_ERR,
0091         .end = IRQ_AA_ERR,
0092         .flags = IORESOURCE_IRQ
0093     }
0094 };
0095
0096 static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
0097
0098 static struct iop_adma_platform_data iop3xx_dma_0_data = {
0099     .hw_id = DMA0_ID,
0100     .pool_size = PAGE_SIZE,
0101 };
0102
0103 static struct iop_adma_platform_data iop3xx_dma_1_data = {
0104     .hw_id = DMA1_ID,
0105     .pool_size = PAGE_SIZE,
0106 };
0107
0108 static struct iop_adma_platform_data iop3xx_aau_data = {
0109     .hw_id = AAU_ID,
0110     .pool_size = 3 * PAGE_SIZE,
0111 };
0112
0113 struct platform_device iop3xx_dma_0_channel = {
0114     .name = "iop-adma",
0115     .id = 0,
0116     .num_resources = 4,
0117     .resource = iop3xx_dma_0_resources,
0118     .dev = {
0119         .dma_mask = &iop3xx_adma_dmamask,
0120         .coherent_dma_mask = DMA_BIT_MASK(32),
0121         .platform_data = (void *) &iop3xx_dma_0_data,
0122     },
0123 };
0124
0125 struct platform_device iop3xx_dma_1_channel = {
0126     .name = "iop-adma",
0127     .id = 1,
0128     .num_resources = 4,
0129     .resource = iop3xx_dma_1_resources,
0130     .dev = {
0131         .dma_mask = &iop3xx_adma_dmamask,
0132         .coherent_dma_mask = DMA_BIT_MASK(32),
0133         .platform_data = (void *) &iop3xx_dma_1_data,
0134     },
0135 };
0136
0137 struct platform_device iop3xx_aau_channel = {
0138     .name = "iop-adma",
0139     .id = 2,
0140     .num_resources = 4,
0141     .resource = iop3xx_aau_resources,
0142     .dev = {
0143         .dma_mask = &iop3xx_adma_dmamask,
0144         .coherent_dma_mask = DMA_BIT_MASK(32),
0145         .platform_data = (void *) &iop3xx_aau_data,
0146     },
0147 };
0148
0149 static int __init iop3xx_adma_cap_init(void)
0150 {
0151     dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
0152     dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
0153
0154     dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
0155     dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
0156
0157     dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
0158     dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
0159
0160     return 0;
0161 }
0162
0163 arch_initcall(iop3xx_adma_cap_init);