arm/mach-imx/tzic.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
0004  */
0005
0006 #include <linux/init.h>
0007 #include <linux/device.h>
0008 #include <linux/errno.h>
0009 #include <linux/io.h>
0010 #include <linux/irqchip.h>
0011 #include <linux/irqdomain.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014
0015 #include <asm/mach/irq.h>
0016 #include <asm/exception.h>
0017
0018 #include "common.h"
0019 #include "hardware.h"
0020 #include "irq-common.h"
0021
0022 /*
0023  *****************************************
0024  * TZIC Registers                        *
0025  *****************************************
0026  */
0027
0028 #define TZIC_INTCNTL    0x0000  /* Control register */
0029 #define TZIC_INTTYPE    0x0004  /* Controller Type register */
0030 #define TZIC_IMPID  0x0008  /* Distributor Implementer Identification */
0031 #define TZIC_PRIOMASK   0x000C  /* Priority Mask Reg */
0032 #define TZIC_SYNCCTRL   0x0010  /* Synchronizer Control register */
0033 #define TZIC_DSMINT 0x0014  /* DSM interrupt Holdoffregister */
0034 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
0035 #define TZIC_ENSET0(i)  (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
0036 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
0037 #define TZIC_SRCSET0    0x0200  /* Source Set Register 0 */
0038 #define TZIC_SRCCLAR0   0x0280  /* Source Clear Register 0 */
0039 #define TZIC_PRIORITY0  0x0400  /* Priority Register 0 */
0040 #define TZIC_PND0   0x0D00  /* Pending Register 0 */
0041 #define TZIC_HIPND(i)   (0x0D80+ ((i) << 2))    /* High Priority Pending Register */
0042 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2))   /* Wakeup Config Register */
0043 #define TZIC_SWINT  0x0F00  /* Software Interrupt Rigger Register */
0044 #define TZIC_ID0    0x0FD0  /* Indentification Register 0 */
0045
0046 static void __iomem *tzic_base;
0047 static struct irq_domain *domain;
0048
0049 #define TZIC_NUM_IRQS 128
0050
0051 #ifdef CONFIG_FIQ
0052 static int tzic_set_irq_fiq(unsigned int hwirq, unsigned int type)
0053 {
0054     unsigned int index, mask, value;
0055
0056     index = hwirq >> 5;
0057     if (unlikely(index >= 4))
0058         return -EINVAL;
0059     mask = 1U << (hwirq & 0x1F);
0060
0061     value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
0062     if (type)
0063         value &= ~mask;
0064     imx_writel(value, tzic_base + TZIC_INTSEC0(index));
0065
0066     return 0;
0067 }
0068 #else
0069 #define tzic_set_irq_fiq NULL
0070 #endif
0071
0072 #ifdef CONFIG_PM
0073 static void tzic_irq_suspend(struct irq_data *d)
0074 {
0075     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0076     int idx = d->hwirq >> 5;
0077
0078     imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
0079 }
0080
0081 static void tzic_irq_resume(struct irq_data *d)
0082 {
0083     int idx = d->hwirq >> 5;
0084
0085     imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
0086            tzic_base + TZIC_WAKEUP0(idx));
0087 }
0088
0089 #else
0090 #define tzic_irq_suspend NULL
0091 #define tzic_irq_resume NULL
0092 #endif
0093
0094 static struct mxc_extra_irq tzic_extra_irq = {
0095 #ifdef CONFIG_FIQ
0096     .set_irq_fiq = tzic_set_irq_fiq,
0097 #endif
0098 };
0099
0100 static __init void tzic_init_gc(int idx, unsigned int irq_start)
0101 {
0102     struct irq_chip_generic *gc;
0103     struct irq_chip_type *ct;
0104
0105     gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
0106                     handle_level_irq);
0107     gc->private = &tzic_extra_irq;
0108     gc->wake_enabled = IRQ_MSK(32);
0109
0110     ct = gc->chip_types;
0111     ct->chip.irq_mask = irq_gc_mask_disable_reg;
0112     ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
0113     ct->chip.irq_set_wake = irq_gc_set_wake;
0114     ct->chip.irq_suspend = tzic_irq_suspend;
0115     ct->chip.irq_resume = tzic_irq_resume;
0116     ct->regs.disable = TZIC_ENCLEAR0(idx);
0117     ct->regs.enable = TZIC_ENSET0(idx);
0118
0119     irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
0120 }
0121
0122 static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
0123 {
0124     u32 stat;
0125     int i, irqofs, handled;
0126
0127     do {
0128         handled = 0;
0129
0130         for (i = 0; i < 4; i++) {
0131             stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
0132                 imx_readl(tzic_base + TZIC_INTSEC0(i));
0133
0134             while (stat) {
0135                 handled = 1;
0136                 irqofs = fls(stat) - 1;
0137                 generic_handle_domain_irq(domain, irqofs + i * 32);
0138                 stat &= ~(1 << irqofs);
0139             }
0140         }
0141     } while (handled);
0142 }
0143
0144 /*
0145  * This function initializes the TZIC hardware and disables all the
0146  * interrupts. It registers the interrupt enable and disable functions
0147  * to the kernel for each interrupt source.
0148  */
0149 static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
0150 {
0151     int irq_base;
0152     int i;
0153
0154     tzic_base = of_iomap(np, 0);
0155     WARN_ON(!tzic_base);
0156
0157     /* put the TZIC into the reset value with
0158      * all interrupts disabled
0159      */
0160     i = imx_readl(tzic_base + TZIC_INTCNTL);
0161
0162     imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
0163     imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
0164     imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
0165
0166     for (i = 0; i < 4; i++)
0167         imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
0168
0169     /* disable all interrupts */
0170     for (i = 0; i < 4; i++)
0171         imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
0172
0173     /* all IRQ no FIQ Warning :: No selection */
0174
0175     irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
0176     WARN_ON(irq_base < 0);
0177
0178     domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
0179                        &irq_domain_simple_ops, NULL);
0180     WARN_ON(!domain);
0181
0182     for (i = 0; i < 4; i++, irq_base += 32)
0183         tzic_init_gc(i, irq_base);
0184
0185     set_handle_irq(tzic_handle_irq);
0186
0187 #ifdef CONFIG_FIQ
0188     /* Initialize FIQ */
0189     init_FIQ(FIQ_START);
0190 #endif
0191
0192     pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
0193
0194     return 0;
0195 }
0196 IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);
0197
0198 /**
0199  * tzic_enable_wake() - enable wakeup interrupt
0200  *
0201  * @return          0 if successful; non-zero otherwise
0202  *
0203  * This function provides an interrupt synchronization point that is required
0204  * by tzic enabled platforms before entering imx specific low power modes (ie,
0205  * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
0206  */
0207 int tzic_enable_wake(void)
0208 {
0209     unsigned int i;
0210
0211     imx_writel(1, tzic_base + TZIC_DSMINT);
0212     if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
0213         return -EAGAIN;
0214
0215     for (i = 0; i < 4; i++)
0216         imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
0217                tzic_base + TZIC_WAKEUP0(i));
0218
0219     return 0;
0220 }