arm/mach-imx/system.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 1999 ARM Limited
0004  * Copyright (C) 2000 Deep Blue Solutions Ltd
0005  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
0006  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
0007  * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/clk.h>
0012 #include <linux/io.h>
0013 #include <linux/err.h>
0014 #include <linux/delay.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017
0018 #include <asm/system_misc.h>
0019 #include <asm/proc-fns.h>
0020 #include <asm/mach-types.h>
0021 #include <asm/hardware/cache-l2x0.h>
0022
0023 #include "common.h"
0024 #include "hardware.h"
0025
0026 static void __iomem *wdog_base;
0027 static struct clk *wdog_clk;
0028 static int wcr_enable = (1 << 2);
0029
0030 /*
0031  * Reset the system. It is called by machine_restart().
0032  */
0033 void mxc_restart(enum reboot_mode mode, const char *cmd)
0034 {
0035     if (!wdog_base)
0036         goto reset_fallback;
0037
0038     if (!IS_ERR(wdog_clk))
0039         clk_enable(wdog_clk);
0040
0041     /* Assert SRS signal */
0042     imx_writew(wcr_enable, wdog_base);
0043     /*
0044      * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
0045      * written twice), we add another two writes to ensure there must be at
0046      * least two writes happen in the same one 32kHz clock period.  We save
0047      * the target check here, since the writes shouldn't be a huge burden
0048      * for other platforms.
0049      */
0050     imx_writew(wcr_enable, wdog_base);
0051     imx_writew(wcr_enable, wdog_base);
0052
0053     /* wait for reset to assert... */
0054     mdelay(500);
0055
0056     pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
0057
0058     /* delay to allow the serial port to show the message */
0059     mdelay(50);
0060
0061 reset_fallback:
0062     /* we'll take a jump through zero as a poor second */
0063     soft_restart(0);
0064 }
0065
0066 void __init mxc_arch_reset_init(void __iomem *base)
0067 {
0068     wdog_base = base;
0069
0070     wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
0071     if (IS_ERR(wdog_clk))
0072         pr_warn("%s: failed to get wdog clock\n", __func__);
0073     else
0074         clk_prepare(wdog_clk);
0075 }
0076
0077 #ifdef CONFIG_SOC_IMX1
0078 void __init imx1_reset_init(void __iomem *base)
0079 {
0080     wcr_enable = (1 << 0);
0081     mxc_arch_reset_init(base);
0082 }
0083 #endif
0084
0085 #ifdef CONFIG_CACHE_L2X0
0086 void __init imx_init_l2cache(void)
0087 {
0088     void __iomem *l2x0_base;
0089     struct device_node *np;
0090     unsigned int val;
0091
0092     np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
0093     if (!np)
0094         return;
0095
0096     l2x0_base = of_iomap(np, 0);
0097     if (!l2x0_base)
0098         goto put_node;
0099
0100     if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
0101         /* Configure the L2 PREFETCH and POWER registers */
0102         val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
0103         val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
0104             L310_PREFETCH_CTRL_INSTR_PREFETCH |
0105             L310_PREFETCH_CTRL_DATA_PREFETCH;
0106
0107         /* Set perfetch offset to improve performance */
0108         val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
0109         val |= 15;
0110
0111         writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
0112     }
0113
0114     iounmap(l2x0_base);
0115 put_node:
0116     of_node_put(np);
0117 }
0118 #endif