arm/mach-imx/src.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2011 Freescale Semiconductor, Inc.
0004  * Copyright 2011 Linaro Ltd.
0005  */
0006
0007 #include <linux/init.h>
0008 #include <linux/io.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/reset-controller.h>
0014 #include <linux/smp.h>
0015 #include <asm/smp_plat.h>
0016 #include "common.h"
0017 #include "hardware.h"
0018
0019 #define SRC_SCR             0x000
0020 #define SRC_GPR1_V1         0x020
0021 #define SRC_GPR1_V2         0x074
0022 #define SRC_GPR1(gpr_v2)        ((gpr_v2) ? SRC_GPR1_V2 : SRC_GPR1_V1)
0023 #define BP_SRC_SCR_WARM_RESET_ENABLE    0
0024 #define BP_SRC_SCR_SW_GPU_RST       1
0025 #define BP_SRC_SCR_SW_VPU_RST       2
0026 #define BP_SRC_SCR_SW_IPU1_RST      3
0027 #define BP_SRC_SCR_SW_OPEN_VG_RST   4
0028 #define BP_SRC_SCR_SW_IPU2_RST      12
0029 #define BP_SRC_SCR_CORE1_RST        14
0030 #define BP_SRC_SCR_CORE1_ENABLE     22
0031 /* below is for i.MX7D */
0032 #define SRC_A7RCR1          0x008
0033 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE   1
0034 #define GPC_CPU_PGC_SW_PUP_REQ      0xf0
0035 #define GPC_CPU_PGC_SW_PDN_REQ      0xfc
0036 #define GPC_PGC_C1          0x840
0037 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7  0x2
0038
0039 static void __iomem *src_base;
0040 static DEFINE_SPINLOCK(scr_lock);
0041 static bool gpr_v2;
0042 static void __iomem *gpc_base;
0043
0044 static const int sw_reset_bits[5] = {
0045     BP_SRC_SCR_SW_GPU_RST,
0046     BP_SRC_SCR_SW_VPU_RST,
0047     BP_SRC_SCR_SW_IPU1_RST,
0048     BP_SRC_SCR_SW_OPEN_VG_RST,
0049     BP_SRC_SCR_SW_IPU2_RST
0050 };
0051
0052 static int imx_src_reset_module(struct reset_controller_dev *rcdev,
0053         unsigned long sw_reset_idx)
0054 {
0055     unsigned long timeout;
0056     unsigned long flags;
0057     int bit;
0058     u32 val;
0059
0060     if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
0061         return -EINVAL;
0062
0063     bit = 1 << sw_reset_bits[sw_reset_idx];
0064
0065     spin_lock_irqsave(&scr_lock, flags);
0066     val = readl_relaxed(src_base + SRC_SCR);
0067     val |= bit;
0068     writel_relaxed(val, src_base + SRC_SCR);
0069     spin_unlock_irqrestore(&scr_lock, flags);
0070
0071     timeout = jiffies + msecs_to_jiffies(1000);
0072     while (readl(src_base + SRC_SCR) & bit) {
0073         if (time_after(jiffies, timeout))
0074             return -ETIME;
0075         cpu_relax();
0076     }
0077
0078     return 0;
0079 }
0080
0081 static const struct reset_control_ops imx_src_ops = {
0082     .reset = imx_src_reset_module,
0083 };
0084
0085 static void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
0086 {
0087     writel_relaxed(enable, gpc_base + offset);
0088 }
0089
0090 /*
0091  * The motivation for bringing up the second i.MX7D core inside the kernel
0092  * is that legacy vendor bootloaders usually do not implement PSCI support.
0093  * This is a significant blocker for systems in the field that are running old
0094  * bootloader versions to upgrade to a modern mainline kernel version, as only
0095  * one CPU of the i.MX7D would be brought up.
0096  * Bring up the second i.MX7D core inside the kernel to make the migration
0097  * path to mainline kernel easier for the existing iMX7D users.
0098  */
0099 void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn)
0100 {
0101     u32 reg = pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ;
0102     u32 val, pup;
0103     int ret;
0104
0105     imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
0106     val = readl_relaxed(gpc_base + reg);
0107     val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
0108     writel_relaxed(val, gpc_base + reg);
0109
0110     ret = readl_relaxed_poll_timeout_atomic(gpc_base + reg, pup,
0111                 !(pup & BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7),
0112                 5, 1000000);
0113     if (ret < 0) {
0114         pr_err("i.MX7D: CORE1_A7 power up timeout\n");
0115         val &= ~BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
0116         writel_relaxed(val, gpc_base + reg);
0117     }
0118
0119     imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
0120 }
0121
0122 void imx_enable_cpu(int cpu, bool enable)
0123 {
0124     u32 mask, val;
0125
0126     cpu = cpu_logical_map(cpu);
0127     spin_lock(&scr_lock);
0128     if (gpr_v2) {
0129         if (enable)
0130             imx_gpcv2_set_core1_pdn_pup_by_software(false);
0131
0132         mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
0133         val = readl_relaxed(src_base + SRC_A7RCR1);
0134         val = enable ? val | mask : val & ~mask;
0135         writel_relaxed(val, src_base + SRC_A7RCR1);
0136     } else {
0137         mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
0138         val = readl_relaxed(src_base + SRC_SCR);
0139         val = enable ? val | mask : val & ~mask;
0140         val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
0141         writel_relaxed(val, src_base + SRC_SCR);
0142     }
0143     spin_unlock(&scr_lock);
0144 }
0145
0146 void imx_set_cpu_jump(int cpu, void *jump_addr)
0147 {
0148     cpu = cpu_logical_map(cpu);
0149     writel_relaxed(__pa_symbol(jump_addr),
0150                src_base + SRC_GPR1(gpr_v2) + cpu * 8);
0151 }
0152
0153 u32 imx_get_cpu_arg(int cpu)
0154 {
0155     cpu = cpu_logical_map(cpu);
0156     return readl_relaxed(src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4);
0157 }
0158
0159 void imx_set_cpu_arg(int cpu, u32 arg)
0160 {
0161     cpu = cpu_logical_map(cpu);
0162     writel_relaxed(arg, src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4);
0163 }
0164
0165 void __init imx_src_init(void)
0166 {
0167     struct device_node *np;
0168     u32 val;
0169
0170     np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
0171     if (!np)
0172         return;
0173     src_base = of_iomap(np, 0);
0174     WARN_ON(!src_base);
0175
0176     /*
0177      * force warm reset sources to generate cold reset
0178      * for a more reliable restart
0179      */
0180     spin_lock(&scr_lock);
0181     val = readl_relaxed(src_base + SRC_SCR);
0182     val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
0183     writel_relaxed(val, src_base + SRC_SCR);
0184     spin_unlock(&scr_lock);
0185 }
0186
0187 void __init imx7_src_init(void)
0188 {
0189     struct device_node *np;
0190
0191     gpr_v2 = true;
0192
0193     np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-src");
0194     if (!np)
0195         return;
0196
0197     src_base = of_iomap(np, 0);
0198     if (!src_base)
0199         return;
0200
0201     np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc");
0202     if (!np)
0203         return;
0204
0205     gpc_base = of_iomap(np, 0);
0206     if (!gpc_base)
0207         return;
0208 }
0209
0210 static const struct of_device_id imx_src_dt_ids[] = {
0211     { .compatible = "fsl,imx51-src" },
0212     { /* sentinel */ }
0213 };
0214
0215 static int imx_src_probe(struct platform_device *pdev)
0216 {
0217     struct reset_controller_dev *rcdev;
0218
0219     rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);
0220     if (!rcdev)
0221         return -ENOMEM;
0222
0223     rcdev->ops = &imx_src_ops;
0224     rcdev->dev = &pdev->dev;
0225     rcdev->of_node = pdev->dev.of_node;
0226     rcdev->nr_resets = ARRAY_SIZE(sw_reset_bits);
0227
0228     return devm_reset_controller_register(&pdev->dev, rcdev);
0229 }
0230
0231 static struct platform_driver imx_src_driver = {
0232     .driver = {
0233         .name = "imx-src",
0234         .of_match_table = imx_src_dt_ids,
0235     },
0236     .probe = imx_src_probe,
0237 };
0238 builtin_platform_driver(imx_src_driver);