arm/mach-imx/mm-imx3.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright (C) 1999,2000 Arm Limited
0004  *  Copyright (C) 2000 Deep Blue Solutions Ltd
0005  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
0006  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
0007  *    - add MX31 specific definitions
0008  */
0009
0010 #include <linux/mm.h>
0011 #include <linux/init.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/of_address.h>
0015 #include <linux/pinctrl/machine.h>
0016
0017 #include <asm/system_misc.h>
0018 #include <asm/hardware/cache-l2x0.h>
0019 #include <asm/mach/map.h>
0020
0021 #include "common.h"
0022 #include "crmregs-imx3.h"
0023 #include "hardware.h"
0024
0025 void __iomem *mx3_ccm_base;
0026
0027 static void imx3_idle(void)
0028 {
0029     unsigned long reg = 0;
0030
0031     __asm__ __volatile__(
0032         /* disable I and D cache */
0033         "mrc p15, 0, %0, c1, c0, 0\n"
0034         "bic %0, %0, #0x00001000\n"
0035         "bic %0, %0, #0x00000004\n"
0036         "mcr p15, 0, %0, c1, c0, 0\n"
0037         /* invalidate I cache */
0038         "mov %0, #0\n"
0039         "mcr p15, 0, %0, c7, c5, 0\n"
0040         /* clear and invalidate D cache */
0041         "mov %0, #0\n"
0042         "mcr p15, 0, %0, c7, c14, 0\n"
0043         /* WFI */
0044         "mov %0, #0\n"
0045         "mcr p15, 0, %0, c7, c0, 4\n"
0046         "nop\n" "nop\n" "nop\n" "nop\n"
0047         "nop\n" "nop\n" "nop\n"
0048         /* enable I and D cache */
0049         "mrc p15, 0, %0, c1, c0, 0\n"
0050         "orr %0, %0, #0x00001000\n"
0051         "orr %0, %0, #0x00000004\n"
0052         "mcr p15, 0, %0, c1, c0, 0\n"
0053         : "=r" (reg));
0054 }
0055
0056 static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
0057                      unsigned int mtype, void *caller)
0058 {
0059     if (mtype == MT_DEVICE) {
0060         /*
0061          * Access all peripherals below 0x80000000 as nonshared device
0062          * on mx3, but leave l2cc alone.  Otherwise cache corruptions
0063          * can occur.
0064          */
0065         if (phys_addr < 0x80000000 &&
0066                 !addr_in_module(phys_addr, MX3x_L2CC))
0067             mtype = MT_DEVICE_NONSHARED;
0068     }
0069
0070     return __arm_ioremap_caller(phys_addr, size, mtype, caller);
0071 }
0072
0073 #ifdef CONFIG_SOC_IMX31
0074 static struct map_desc mx31_io_desc[] __initdata = {
0075     imx_map_entry(MX31, X_MEMC, MT_DEVICE),
0076     imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
0077     imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
0078     imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
0079     imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
0080 };
0081
0082 /*
0083  * This function initializes the memory map. It is called during the
0084  * system startup to create static physical to virtual memory mappings
0085  * for the IO modules.
0086  */
0087 void __init mx31_map_io(void)
0088 {
0089     iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
0090 }
0091
0092 static void imx31_idle(void)
0093 {
0094     int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
0095     reg &= ~MXC_CCM_CCMR_LPM_MASK;
0096     imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
0097
0098     imx3_idle();
0099 }
0100
0101 void __init imx31_init_early(void)
0102 {
0103     struct device_node *np;
0104
0105     mxc_set_cpu_type(MXC_CPU_MX31);
0106     arch_ioremap_caller = imx3_ioremap_caller;
0107     arm_pm_idle = imx31_idle;
0108     np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
0109     mx3_ccm_base = of_iomap(np, 0);
0110     BUG_ON(!mx3_ccm_base);
0111 }
0112 #endif /* ifdef CONFIG_SOC_IMX31 */
0113
0114 #ifdef CONFIG_SOC_IMX35
0115 static struct map_desc mx35_io_desc[] __initdata = {
0116     imx_map_entry(MX35, X_MEMC, MT_DEVICE),
0117     imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
0118     imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
0119     imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
0120     imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
0121 };
0122
0123 void __init mx35_map_io(void)
0124 {
0125     iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
0126 }
0127
0128 static void imx35_idle(void)
0129 {
0130     int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR);
0131     reg &= ~MXC_CCM_CCMR_LPM_MASK;
0132     reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
0133     imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
0134
0135     imx3_idle();
0136 }
0137
0138 void __init imx35_init_early(void)
0139 {
0140     struct device_node *np;
0141
0142     mxc_set_cpu_type(MXC_CPU_MX35);
0143     arm_pm_idle = imx35_idle;
0144     arch_ioremap_caller = imx3_ioremap_caller;
0145     np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm");
0146     mx3_ccm_base = of_iomap(np, 0);
0147     BUG_ON(!mx3_ccm_base);
0148 }
0149 #endif /* ifdef CONFIG_SOC_IMX35 */