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0005 #include <linux/irqchip.h>
0006 #include <linux/mfd/syscon.h>
0007 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
0008 #include <linux/micrel_phy.h>
0009 #include <linux/of_platform.h>
0010 #include <linux/phy.h>
0011 #include <linux/regmap.h>
0012 #include <asm/mach/arch.h>
0013 #include <asm/mach/map.h>
0014
0015 #include "common.h"
0016 #include "cpuidle.h"
0017 #include "hardware.h"
0018
0019 static void __init imx6ul_enet_clk_init(void)
0020 {
0021 struct regmap *gpr;
0022
0023 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
0024 if (!IS_ERR(gpr))
0025 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
0026 IMX6UL_GPR1_ENET_CLK_OUTPUT);
0027 else
0028 pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
0029 }
0030
0031 static inline void imx6ul_enet_init(void)
0032 {
0033 imx6ul_enet_clk_init();
0034 }
0035
0036 static void __init imx6ul_init_machine(void)
0037 {
0038 imx_print_silicon_rev(cpu_is_imx6ull() ? "i.MX6ULL" : "i.MX6UL",
0039 imx_get_soc_revision());
0040
0041 of_platform_default_populate(NULL, NULL, NULL);
0042 imx6ul_enet_init();
0043 imx_anatop_init();
0044 imx6ul_pm_init();
0045 }
0046
0047 static void __init imx6ul_init_irq(void)
0048 {
0049 imx_init_revision_from_anatop();
0050 imx_src_init();
0051 irqchip_init();
0052 imx6_pm_ccm_init("fsl,imx6ul-ccm");
0053 }
0054
0055 static void __init imx6ul_init_late(void)
0056 {
0057 imx6sx_cpuidle_init();
0058
0059 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
0060 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
0061 }
0062
0063 static const char * const imx6ul_dt_compat[] __initconst = {
0064 "fsl,imx6ul",
0065 "fsl,imx6ull",
0066 NULL,
0067 };
0068
0069 DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
0070 .init_irq = imx6ul_init_irq,
0071 .init_machine = imx6ul_init_machine,
0072 .init_late = imx6ul_init_late,
0073 .dt_compat = imx6ul_dt_compat,
0074 MACHINE_END