arm/mach-imx/iim.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
0004  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
0005  */
0006
0007 #ifndef __ASM_ARCH_MXC_IIM_H__
0008 #define __ASM_ARCH_MXC_IIM_H__
0009
0010 /* Register offsets */
0011 #define MXC_IIMSTAT             0x0000
0012 #define MXC_IIMSTATM            0x0004
0013 #define MXC_IIMERR              0x0008
0014 #define MXC_IIMEMASK            0x000C
0015 #define MXC_IIMFCTL             0x0010
0016 #define MXC_IIMUA               0x0014
0017 #define MXC_IIMLA               0x0018
0018 #define MXC_IIMSDAT             0x001C
0019 #define MXC_IIMPREV             0x0020
0020 #define MXC_IIMSREV             0x0024
0021 #define MXC_IIMPRG_P            0x0028
0022 #define MXC_IIMSCS0             0x002C
0023 #define MXC_IIMSCS1             0x0030
0024 #define MXC_IIMSCS2             0x0034
0025 #define MXC_IIMSCS3             0x0038
0026 #define MXC_IIMFBAC0            0x0800
0027 #define MXC_IIMJAC              0x0804
0028 #define MXC_IIMHWV1             0x0808
0029 #define MXC_IIMHWV2             0x080C
0030 #define MXC_IIMHAB0             0x0810
0031 #define MXC_IIMHAB1             0x0814
0032 /* Definitions for i.MX27 TO2 */
0033 #define MXC_IIMMAC              0x0814
0034 #define MXC_IIMPREV_FUSE        0x0818
0035 #define MXC_IIMSREV_FUSE        0x081C
0036 #define MXC_IIMSJC_CHALL_0      0x0820
0037 #define MXC_IIMSJC_CHALL_7      0x083C
0038 #define MXC_IIMFB0UC17          0x0840
0039 #define MXC_IIMFB0UC255         0x0BFC
0040 #define MXC_IIMFBAC1            0x0C00
0041 /* Definitions for i.MX27 TO2 */
0042 #define MXC_IIMSUID             0x0C04
0043 #define MXC_IIMKEY0             0x0C04
0044 #define MXC_IIMKEY20            0x0C54
0045 #define MXC_IIMSJC_RESP_0       0x0C58
0046 #define MXC_IIMSJC_RESP_7       0x0C74
0047 #define MXC_IIMFB1UC30          0x0C78
0048 #define MXC_IIMFB1UC255         0x0FFC
0049
0050 /* Bit definitions */
0051
0052 #define MXC_IIMHWV1_WLOCK               (0x1 << 7)
0053 #define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
0054 #define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
0055 #define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
0056 #define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
0057 #define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
0058 #define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
0059
0060 #define MXC_IIMHWV2_WLOCK               (0x1 << 7)
0061 #define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
0062 #define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
0063
0064 #endif /* __ASM_ARCH_MXC_IIM_H__ */