arm/mach-imx/gpc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2011-2013 Freescale Semiconductor, Inc.
0004  * Copyright 2011 Linaro Ltd.
0005  */
0006
0007 #include <linux/io.h>
0008 #include <linux/irq.h>
0009 #include <linux/irqchip.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_irq.h>
0013
0014 #include "common.h"
0015 #include "hardware.h"
0016
0017 #define GPC_CNTR        0x0
0018 #define GPC_IMR1        0x008
0019 #define GPC_PGC_CPU_PDN     0x2a0
0020 #define GPC_PGC_CPU_PUPSCR  0x2a4
0021 #define GPC_PGC_CPU_PDNSCR  0x2a8
0022 #define GPC_PGC_SW2ISO_SHIFT    0x8
0023 #define GPC_PGC_SW_SHIFT    0x0
0024
0025 #define GPC_CNTR_L2_PGE_SHIFT   22
0026
0027 #define IMR_NUM         4
0028 #define GPC_MAX_IRQS        (IMR_NUM * 32)
0029
0030 static void __iomem *gpc_base;
0031 static u32 gpc_wake_irqs[IMR_NUM];
0032 static u32 gpc_saved_imrs[IMR_NUM];
0033
0034 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
0035 {
0036     writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
0037         (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
0038 }
0039
0040 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
0041 {
0042     writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
0043         (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
0044 }
0045
0046 void imx_gpc_set_arm_power_in_lpm(bool power_off)
0047 {
0048     writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
0049 }
0050
0051 void imx_gpc_set_l2_mem_power_in_lpm(bool power_off)
0052 {
0053     u32 val;
0054
0055     val = readl_relaxed(gpc_base + GPC_CNTR);
0056     val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT);
0057     if (power_off)
0058         val |= 1 << GPC_CNTR_L2_PGE_SHIFT;
0059     writel_relaxed(val, gpc_base + GPC_CNTR);
0060 }
0061
0062 void imx_gpc_pre_suspend(bool arm_power_off)
0063 {
0064     void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
0065     int i;
0066
0067     /* Tell GPC to power off ARM core when suspend */
0068     if (arm_power_off)
0069         imx_gpc_set_arm_power_in_lpm(arm_power_off);
0070
0071     for (i = 0; i < IMR_NUM; i++) {
0072         gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
0073         writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
0074     }
0075 }
0076
0077 void imx_gpc_post_resume(void)
0078 {
0079     void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
0080     int i;
0081
0082     /* Keep ARM core powered on for other low-power modes */
0083     imx_gpc_set_arm_power_in_lpm(false);
0084
0085     for (i = 0; i < IMR_NUM; i++)
0086         writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
0087 }
0088
0089 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
0090 {
0091     unsigned int idx = d->hwirq / 32;
0092     u32 mask;
0093
0094     mask = 1 << d->hwirq % 32;
0095     gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
0096                   gpc_wake_irqs[idx] & ~mask;
0097
0098     /*
0099      * Do *not* call into the parent, as the GIC doesn't have any
0100      * wake-up facility...
0101      */
0102     return 0;
0103 }
0104
0105 void imx_gpc_mask_all(void)
0106 {
0107     void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
0108     int i;
0109
0110     for (i = 0; i < IMR_NUM; i++) {
0111         gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
0112         writel_relaxed(~0, reg_imr1 + i * 4);
0113     }
0114 }
0115
0116 void imx_gpc_restore_all(void)
0117 {
0118     void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
0119     int i;
0120
0121     for (i = 0; i < IMR_NUM; i++)
0122         writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
0123 }
0124
0125 void imx_gpc_hwirq_unmask(unsigned int hwirq)
0126 {
0127     void __iomem *reg;
0128     u32 val;
0129
0130     reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
0131     val = readl_relaxed(reg);
0132     val &= ~(1 << hwirq % 32);
0133     writel_relaxed(val, reg);
0134 }
0135
0136 void imx_gpc_hwirq_mask(unsigned int hwirq)
0137 {
0138     void __iomem *reg;
0139     u32 val;
0140
0141     reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
0142     val = readl_relaxed(reg);
0143     val |= 1 << (hwirq % 32);
0144     writel_relaxed(val, reg);
0145 }
0146
0147 static void imx_gpc_irq_unmask(struct irq_data *d)
0148 {
0149     imx_gpc_hwirq_unmask(d->hwirq);
0150     irq_chip_unmask_parent(d);
0151 }
0152
0153 static void imx_gpc_irq_mask(struct irq_data *d)
0154 {
0155     imx_gpc_hwirq_mask(d->hwirq);
0156     irq_chip_mask_parent(d);
0157 }
0158
0159 static struct irq_chip imx_gpc_chip = {
0160     .name           = "GPC",
0161     .irq_eoi        = irq_chip_eoi_parent,
0162     .irq_mask       = imx_gpc_irq_mask,
0163     .irq_unmask     = imx_gpc_irq_unmask,
0164     .irq_retrigger      = irq_chip_retrigger_hierarchy,
0165     .irq_set_wake       = imx_gpc_irq_set_wake,
0166     .irq_set_type           = irq_chip_set_type_parent,
0167 #ifdef CONFIG_SMP
0168     .irq_set_affinity   = irq_chip_set_affinity_parent,
0169 #endif
0170 };
0171
0172 static int imx_gpc_domain_translate(struct irq_domain *d,
0173                     struct irq_fwspec *fwspec,
0174                     unsigned long *hwirq,
0175                     unsigned int *type)
0176 {
0177     if (is_of_node(fwspec->fwnode)) {
0178         if (fwspec->param_count != 3)
0179             return -EINVAL;
0180
0181         /* No PPI should point to this domain */
0182         if (fwspec->param[0] != 0)
0183             return -EINVAL;
0184
0185         *hwirq = fwspec->param[1];
0186         *type = fwspec->param[2];
0187         return 0;
0188     }
0189
0190     return -EINVAL;
0191 }
0192
0193 static int imx_gpc_domain_alloc(struct irq_domain *domain,
0194                   unsigned int irq,
0195                   unsigned int nr_irqs, void *data)
0196 {
0197     struct irq_fwspec *fwspec = data;
0198     struct irq_fwspec parent_fwspec;
0199     irq_hw_number_t hwirq;
0200     int i;
0201
0202     if (fwspec->param_count != 3)
0203         return -EINVAL; /* Not GIC compliant */
0204     if (fwspec->param[0] != 0)
0205         return -EINVAL; /* No PPI should point to this domain */
0206
0207     hwirq = fwspec->param[1];
0208     if (hwirq >= GPC_MAX_IRQS)
0209         return -EINVAL; /* Can't deal with this */
0210
0211     for (i = 0; i < nr_irqs; i++)
0212         irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
0213                           &imx_gpc_chip, NULL);
0214
0215     parent_fwspec = *fwspec;
0216     parent_fwspec.fwnode = domain->parent->fwnode;
0217     return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
0218                         &parent_fwspec);
0219 }
0220
0221 static const struct irq_domain_ops imx_gpc_domain_ops = {
0222     .translate  = imx_gpc_domain_translate,
0223     .alloc      = imx_gpc_domain_alloc,
0224     .free       = irq_domain_free_irqs_common,
0225 };
0226
0227 static int __init imx_gpc_init(struct device_node *node,
0228                    struct device_node *parent)
0229 {
0230     struct irq_domain *parent_domain, *domain;
0231     int i;
0232
0233     if (!parent) {
0234         pr_err("%pOF: no parent, giving up\n", node);
0235         return -ENODEV;
0236     }
0237
0238     parent_domain = irq_find_host(parent);
0239     if (!parent_domain) {
0240         pr_err("%pOF: unable to obtain parent domain\n", node);
0241         return -ENXIO;
0242     }
0243
0244     gpc_base = of_iomap(node, 0);
0245     if (WARN_ON(!gpc_base))
0246             return -ENOMEM;
0247
0248     domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
0249                       node, &imx_gpc_domain_ops,
0250                       NULL);
0251     if (!domain) {
0252         iounmap(gpc_base);
0253         return -ENOMEM;
0254     }
0255
0256     /* Initially mask all interrupts */
0257     for (i = 0; i < IMR_NUM; i++)
0258         writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
0259
0260     /*
0261      * Clear the OF_POPULATED flag set in of_irq_init so that
0262      * later the GPC power domain driver will not be skipped.
0263      */
0264     of_node_clear_flag(node, OF_POPULATED);
0265
0266     return 0;
0267 }
0268 IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
0269
0270 void __init imx_gpc_check_dt(void)
0271 {
0272     struct device_node *np;
0273
0274     np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
0275     if (WARN_ON(!np))
0276         return;
0277
0278     if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
0279         pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
0280
0281         /* map GPC, so that at least CPUidle and WARs keep working */
0282         gpc_base = of_iomap(np, 0);
0283     }
0284     of_node_put(np);
0285 }