arm/mach-imx/cpu.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/err.h>
0003 #include <linux/module.h>
0004 #include <linux/io.h>
0005 #include <linux/of.h>
0006 #include <linux/of_address.h>
0007
0008 #include "hardware.h"
0009 #include "common.h"
0010
0011 unsigned int __mxc_cpu_type;
0012 static unsigned int imx_soc_revision;
0013
0014 void mxc_set_cpu_type(unsigned int type)
0015 {
0016     __mxc_cpu_type = type;
0017 }
0018
0019 void imx_set_soc_revision(unsigned int rev)
0020 {
0021     imx_soc_revision = rev;
0022 }
0023
0024 unsigned int imx_get_soc_revision(void)
0025 {
0026     return imx_soc_revision;
0027 }
0028
0029 void imx_print_silicon_rev(const char *cpu, int srev)
0030 {
0031     if (srev == IMX_CHIP_REVISION_UNKNOWN)
0032         pr_info("CPU identified as %s, unknown revision\n", cpu);
0033     else
0034         pr_info("CPU identified as %s, silicon rev %d.%d\n",
0035                 cpu, (srev >> 4) & 0xf, srev & 0xf);
0036 }
0037
0038 void __init imx_set_aips(void __iomem *base)
0039 {
0040     unsigned int reg;
0041 /*
0042  * Set all MPROTx to be non-bufferable, trusted for R/W,
0043  * not forced to user-mode.
0044  */
0045     imx_writel(0x77777777, base + 0x0);
0046     imx_writel(0x77777777, base + 0x4);
0047
0048 /*
0049  * Set all OPACRx to be non-bufferable, to not require
0050  * supervisor privilege level for access, allow for
0051  * write access and untrusted master access.
0052  */
0053     imx_writel(0x0, base + 0x40);
0054     imx_writel(0x0, base + 0x44);
0055     imx_writel(0x0, base + 0x48);
0056     imx_writel(0x0, base + 0x4C);
0057     reg = imx_readl(base + 0x50) & 0x00FFFFFF;
0058     imx_writel(reg, base + 0x50);
0059 }
0060
0061 void __init imx_aips_allow_unprivileged_access(
0062         const char *compat)
0063 {
0064     void __iomem *aips_base_addr;
0065     struct device_node *np;
0066
0067     for_each_compatible_node(np, NULL, compat) {
0068         aips_base_addr = of_iomap(np, 0);
0069         WARN_ON(!aips_base_addr);
0070         imx_set_aips(aips_base_addr);
0071     }
0072 }