arm/mach-imx/avic.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
0004  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
0005  */
0006
0007 #include <linux/module.h>
0008 #include <linux/irq.h>
0009 #include <linux/irqdomain.h>
0010 #include <linux/irqchip.h>
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <asm/mach/irq.h>
0015 #include <asm/exception.h>
0016
0017 #include "common.h"
0018 #include "hardware.h"
0019 #include "irq-common.h"
0020
0021 #define AVIC_INTCNTL        0x00    /* int control reg */
0022 #define AVIC_NIMASK     0x04    /* int mask reg */
0023 #define AVIC_INTENNUM       0x08    /* int enable number reg */
0024 #define AVIC_INTDISNUM      0x0C    /* int disable number reg */
0025 #define AVIC_INTENABLEH     0x10    /* int enable reg high */
0026 #define AVIC_INTENABLEL     0x14    /* int enable reg low */
0027 #define AVIC_INTTYPEH       0x18    /* int type reg high */
0028 #define AVIC_INTTYPEL       0x1C    /* int type reg low */
0029 #define AVIC_NIPRIORITY(x)  (0x20 + 4 * (7 - (x))) /* int priority */
0030 #define AVIC_NIVECSR        0x40    /* norm int vector/status */
0031 #define AVIC_FIVECSR        0x44    /* fast int vector/status */
0032 #define AVIC_INTSRCH        0x48    /* int source reg high */
0033 #define AVIC_INTSRCL        0x4C    /* int source reg low */
0034 #define AVIC_INTFRCH        0x50    /* int force reg high */
0035 #define AVIC_INTFRCL        0x54    /* int force reg low */
0036 #define AVIC_NIPNDH     0x58    /* norm int pending high */
0037 #define AVIC_NIPNDL     0x5C    /* norm int pending low */
0038 #define AVIC_FIPNDH     0x60    /* fast int pending high */
0039 #define AVIC_FIPNDL     0x64    /* fast int pending low */
0040
0041 #define AVIC_NUM_IRQS 64
0042
0043 /* low power interrupt mask registers */
0044 #define MX25_CCM_LPIMR0 0x68
0045 #define MX25_CCM_LPIMR1 0x6C
0046
0047 static void __iomem *avic_base;
0048 static void __iomem *mx25_ccm_base;
0049 static struct irq_domain *domain;
0050
0051 #ifdef CONFIG_FIQ
0052 static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type)
0053 {
0054     unsigned int irqt;
0055
0056     if (hwirq >= AVIC_NUM_IRQS)
0057         return -EINVAL;
0058
0059     if (hwirq < AVIC_NUM_IRQS / 2) {
0060         irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);
0061         imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);
0062     } else {
0063         hwirq -= AVIC_NUM_IRQS / 2;
0064         irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);
0065         imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);
0066     }
0067
0068     return 0;
0069 }
0070 #endif /* CONFIG_FIQ */
0071
0072
0073 static struct mxc_extra_irq avic_extra_irq = {
0074 #ifdef CONFIG_FIQ
0075     .set_irq_fiq = avic_set_irq_fiq,
0076 #endif
0077 };
0078
0079 #ifdef CONFIG_PM
0080 static u32 avic_saved_mask_reg[2];
0081
0082 static void avic_irq_suspend(struct irq_data *d)
0083 {
0084     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0085     struct irq_chip_type *ct = gc->chip_types;
0086     int idx = d->hwirq >> 5;
0087
0088     avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
0089     imx_writel(gc->wake_active, avic_base + ct->regs.mask);
0090
0091     if (mx25_ccm_base) {
0092         u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
0093             MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
0094         /*
0095          * The interrupts which are still enabled will be used as wakeup
0096          * sources. Allow those interrupts in low-power mode.
0097          * The LPIMR registers use 0 to allow an interrupt, the AVIC
0098          * registers use 1.
0099          */
0100         imx_writel(~gc->wake_active, mx25_ccm_base + offs);
0101     }
0102 }
0103
0104 static void avic_irq_resume(struct irq_data *d)
0105 {
0106     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0107     struct irq_chip_type *ct = gc->chip_types;
0108     int idx = d->hwirq >> 5;
0109
0110     imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
0111
0112     if (mx25_ccm_base) {
0113         u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
0114             MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
0115
0116         imx_writel(0xffffffff, mx25_ccm_base + offs);
0117     }
0118 }
0119
0120 #else
0121 #define avic_irq_suspend NULL
0122 #define avic_irq_resume NULL
0123 #endif
0124
0125 static __init void avic_init_gc(int idx, unsigned int irq_start)
0126 {
0127     struct irq_chip_generic *gc;
0128     struct irq_chip_type *ct;
0129
0130     gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
0131                     handle_level_irq);
0132     gc->private = &avic_extra_irq;
0133     gc->wake_enabled = IRQ_MSK(32);
0134
0135     ct = gc->chip_types;
0136     ct->chip.irq_mask = irq_gc_mask_clr_bit;
0137     ct->chip.irq_unmask = irq_gc_mask_set_bit;
0138     ct->chip.irq_ack = irq_gc_mask_clr_bit;
0139     ct->chip.irq_set_wake = irq_gc_set_wake;
0140     ct->chip.irq_suspend = avic_irq_suspend;
0141     ct->chip.irq_resume = avic_irq_resume;
0142     ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
0143     ct->regs.ack = ct->regs.mask;
0144
0145     irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
0146 }
0147
0148 static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
0149 {
0150     u32 nivector;
0151
0152     do {
0153         nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
0154         if (nivector == 0xffff)
0155             break;
0156
0157         generic_handle_domain_irq(domain, nivector);
0158     } while (1);
0159 }
0160
0161 /*
0162  * This function initializes the AVIC hardware and disables all the
0163  * interrupts. It registers the interrupt enable and disable functions
0164  * to the kernel for each interrupt source.
0165  */
0166 static void __init mxc_init_irq(void __iomem *irqbase)
0167 {
0168     struct device_node *np;
0169     int irq_base;
0170     int i;
0171
0172     avic_base = irqbase;
0173
0174     np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
0175     mx25_ccm_base = of_iomap(np, 0);
0176
0177     if (mx25_ccm_base) {
0178         /*
0179          * By default, we mask all interrupts. We set the actual mask
0180          * before we go into low-power mode.
0181          */
0182         imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);
0183         imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);
0184     }
0185
0186     /* put the AVIC into the reset value with
0187      * all interrupts disabled
0188      */
0189     imx_writel(0, avic_base + AVIC_INTCNTL);
0190     imx_writel(0x1f, avic_base + AVIC_NIMASK);
0191
0192     /* disable all interrupts */
0193     imx_writel(0, avic_base + AVIC_INTENABLEH);
0194     imx_writel(0, avic_base + AVIC_INTENABLEL);
0195
0196     /* all IRQ no FIQ */
0197     imx_writel(0, avic_base + AVIC_INTTYPEH);
0198     imx_writel(0, avic_base + AVIC_INTTYPEL);
0199
0200     irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
0201     WARN_ON(irq_base < 0);
0202
0203     np = of_find_compatible_node(NULL, NULL, "fsl,avic");
0204     domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
0205                        &irq_domain_simple_ops, NULL);
0206     WARN_ON(!domain);
0207
0208     for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
0209         avic_init_gc(i, irq_base);
0210
0211     /* Set default priority value (0) for all IRQ's */
0212     for (i = 0; i < 8; i++)
0213         imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
0214
0215     set_handle_irq(avic_handle_irq);
0216
0217 #ifdef CONFIG_FIQ
0218     /* Initialize FIQ */
0219     init_FIQ(FIQ_START);
0220 #endif
0221
0222     printk(KERN_INFO "MXC IRQ initialized\n");
0223 }
0224
0225 static int __init imx_avic_init(struct device_node *node,
0226                    struct device_node *parent)
0227 {
0228     void __iomem *avic_base;
0229
0230     avic_base = of_iomap(node, 0);
0231     BUG_ON(!avic_base);
0232     mxc_init_irq(avic_base);
0233     return 0;
0234 }
0235
0236 IRQCHIP_DECLARE(imx_avic, "fsl,avic", imx_avic_init);