arm/mach-highbank/sysregs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2011 Calxeda, Inc.
0004  */
0005 #ifndef _MACH_HIGHBANK__SYSREGS_H_
0006 #define _MACH_HIGHBANK__SYSREGS_H_
0007
0008 #include <linux/io.h>
0009 #include <linux/smp.h>
0010 #include <asm/smp_plat.h>
0011 #include <asm/smp_scu.h>
0012 #include "core.h"
0013
0014 extern void __iomem *sregs_base;
0015
0016 #define HB_SREG_A9_PWR_REQ      0xf00
0017 #define HB_SREG_A9_BOOT_STAT        0xf04
0018 #define HB_SREG_A9_BOOT_DATA        0xf08
0019
0020 #define HB_PWR_SUSPEND          0
0021 #define HB_PWR_SOFT_RESET       1
0022 #define HB_PWR_HARD_RESET       2
0023 #define HB_PWR_SHUTDOWN         3
0024
0025 #define SREG_CPU_PWR_CTRL(c)        (0x200 + ((c) * 4))
0026
0027 static inline void highbank_set_core_pwr(void)
0028 {
0029     int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
0030     if (scu_base_addr)
0031         scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
0032     else
0033         writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
0034 }
0035
0036 static inline void highbank_clear_core_pwr(void)
0037 {
0038     int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
0039     if (scu_base_addr)
0040         scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
0041     else
0042         writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
0043 }
0044
0045 static inline void highbank_set_pwr_suspend(void)
0046 {
0047     writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
0048     highbank_set_core_pwr();
0049 }
0050
0051 static inline void highbank_set_pwr_shutdown(void)
0052 {
0053     writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
0054     highbank_set_core_pwr();
0055 }
0056
0057 static inline void highbank_set_pwr_soft_reset(void)
0058 {
0059     writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
0060     highbank_set_core_pwr();
0061 }
0062
0063 static inline void highbank_set_pwr_hard_reset(void)
0064 {
0065     writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
0066     highbank_set_core_pwr();
0067 }
0068
0069 static inline void highbank_clear_pwr_request(void)
0070 {
0071     writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
0072     highbank_clear_core_pwr();
0073 }
0074
0075 #endif