include/mach/hardware.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/mach-footbridge/include/mach/hardware.h
0004  *
0005  *  Copyright (C) 1998-1999 Russell King.
0006  *
0007  *  This file contains the hardware definitions of the EBSA-285.
0008  */
0009 #ifndef __ASM_ARCH_HARDWARE_H
0010 #define __ASM_ARCH_HARDWARE_H
0011
0012 /*   Virtual      Physical  Size
0013  * 0xff800000   0x40000000  1MB X-Bus
0014  * 0xff000000   0x7c000000  1MB PCI I/O space
0015  * 0xfe000000   0x42000000  1MB CSR
0016  * 0xfd000000   0x78000000  1MB Outbound write flush (not supported)
0017  * 0xfc000000   0x79000000  1MB PCI IACK/special space
0018  * 0xfb000000   0x7a000000  16MB    PCI Config type 1
0019  * 0xfa000000   0x7b000000  16MB    PCI Config type 0
0020  * 0xf9000000   0x50000000  1MB Cache flush
0021  * 0xf0000000   0x80000000  16MB    ISA memory
0022  */
0023
0024 #define XBUS_SIZE       0x00100000
0025 #define XBUS_BASE       0xff800000
0026
0027 #define ARMCSR_SIZE     0x00100000
0028 #define ARMCSR_BASE     0xfe000000
0029
0030 #define WFLUSH_SIZE     0x00100000
0031 #define WFLUSH_BASE     0xfd000000
0032
0033 #define PCIIACK_SIZE        0x00100000
0034 #define PCIIACK_BASE        0xfc000000
0035
0036 #define PCICFG1_SIZE        0x01000000
0037 #define PCICFG1_BASE        0xfb000000
0038
0039 #define PCICFG0_SIZE        0x01000000
0040 #define PCICFG0_BASE        0xfa000000
0041
0042 #define PCIMEM_SIZE     0x01000000
0043 #define PCIMEM_BASE     0xf0000000
0044
0045 #define XBUS_CS2        0x40012000
0046
0047 #define XBUS_SWITCH     ((volatile unsigned char *)(XBUS_BASE + 0x12000))
0048 #define XBUS_SWITCH_SWITCH  ((*XBUS_SWITCH) & 15)
0049 #define XBUS_SWITCH_J17_13  ((*XBUS_SWITCH) & (1 << 4))
0050 #define XBUS_SWITCH_J17_11  ((*XBUS_SWITCH) & (1 << 5))
0051 #define XBUS_SWITCH_J17_9   ((*XBUS_SWITCH) & (1 << 6))
0052
0053 #define UNCACHEABLE_ADDR    (ARMCSR_BASE + 0x108)   /* CSR_ROMBASEMASK */
0054
0055
0056 /* PIC irq control */
0057 #define PIC_LO          0x20
0058 #define PIC_MASK_LO     0x21
0059 #define PIC_HI          0xA0
0060 #define PIC_MASK_HI     0xA1
0061
0062 /* GPIO pins */
0063 #define GPIO_CCLK       0x800
0064 #define GPIO_DSCLK      0x400
0065 #define GPIO_E2CLK      0x200
0066 #define GPIO_IOLOAD     0x100
0067 #define GPIO_RED_LED        0x080
0068 #define GPIO_WDTIMER        0x040
0069 #define GPIO_DATA       0x020
0070 #define GPIO_IOCLK      0x010
0071 #define GPIO_DONE       0x008
0072 #define GPIO_FAN        0x004
0073 #define GPIO_GREEN_LED      0x002
0074 #define GPIO_RESET      0x001
0075
0076 /* CPLD pins */
0077 #define CPLD_DS_ENABLE      8
0078 #define CPLD_7111_DISABLE   4
0079 #define CPLD_UNMUTE     2
0080 #define CPLD_FLASH_WR_ENABLE    1
0081
0082 #ifndef __ASSEMBLY__
0083 extern raw_spinlock_t nw_gpio_lock;
0084 extern void nw_gpio_modify_op(unsigned int mask, unsigned int set);
0085 extern void nw_gpio_modify_io(unsigned int mask, unsigned int in);
0086 extern unsigned int nw_gpio_read(void);
0087 extern void nw_cpld_modify(unsigned int mask, unsigned int set);
0088 #endif
0089
0090 #endif