arm/mach-footbridge/dc21285.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285
0004  *
0005  *  Copyright (C) 1998-2001 Russell King
0006  *  Copyright (C) 1998-2000 Phil Blundell
0007  */
0008 #include <linux/kernel.h>
0009 #include <linux/pci.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/mm.h>
0012 #include <linux/slab.h>
0013 #include <linux/init.h>
0014 #include <linux/ioport.h>
0015 #include <linux/irq.h>
0016 #include <linux/io.h>
0017 #include <linux/spinlock.h>
0018
0019 #include <asm/irq.h>
0020 #include <asm/mach/pci.h>
0021 #include <asm/hardware/dec21285.h>
0022
0023 #define MAX_SLOTS       21
0024
0025 #define PCICMD_ABORT        ((PCI_STATUS_REC_MASTER_ABORT| \
0026                   PCI_STATUS_REC_TARGET_ABORT)<<16)
0027
0028 #define PCICMD_ERROR_BITS   ((PCI_STATUS_DETECTED_PARITY | \
0029                   PCI_STATUS_REC_MASTER_ABORT | \
0030                   PCI_STATUS_REC_TARGET_ABORT | \
0031                   PCI_STATUS_PARITY) << 16)
0032
0033 extern int setup_arm_irq(int, struct irqaction *);
0034
0035 static unsigned long
0036 dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
0037 {
0038     unsigned long addr = 0;
0039
0040     if (bus->number == 0) {
0041         if (PCI_SLOT(devfn) == 0)
0042             /*
0043              * For devfn 0, point at the 21285
0044              */
0045             addr = ARMCSR_BASE;
0046         else {
0047             devfn -= 1 << 3;
0048
0049             if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
0050                 addr = PCICFG0_BASE | 0xc00000 | (devfn << 8);
0051         }
0052     } else
0053         addr = PCICFG1_BASE | (bus->number << 16) | (devfn << 8);
0054
0055     return addr;
0056 }
0057
0058 static int
0059 dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
0060             int size, u32 *value)
0061 {
0062     unsigned long addr = dc21285_base_address(bus, devfn);
0063     u32 v = 0xffffffff;
0064
0065     if (addr)
0066         switch (size) {
0067         case 1:
0068             asm volatile("ldrb  %0, [%1, %2]"
0069                 : "=r" (v) : "r" (addr), "r" (where) : "cc");
0070             break;
0071         case 2:
0072             asm volatile("ldrh  %0, [%1, %2]"
0073                 : "=r" (v) : "r" (addr), "r" (where) : "cc");
0074             break;
0075         case 4:
0076             asm volatile("ldr   %0, [%1, %2]"
0077                 : "=r" (v) : "r" (addr), "r" (where) : "cc");
0078             break;
0079         }
0080
0081     *value = v;
0082
0083     v = *CSR_PCICMD;
0084     if (v & PCICMD_ABORT) {
0085         *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
0086         return -1;
0087     }
0088
0089     return PCIBIOS_SUCCESSFUL;
0090 }
0091
0092 static int
0093 dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
0094              int size, u32 value)
0095 {
0096     unsigned long addr = dc21285_base_address(bus, devfn);
0097     u32 v;
0098
0099     if (addr)
0100         switch (size) {
0101         case 1:
0102             asm volatile("strb  %0, [%1, %2]"
0103                 : : "r" (value), "r" (addr), "r" (where)
0104                 : "cc");
0105             break;
0106         case 2:
0107             asm volatile("strh  %0, [%1, %2]"
0108                 : : "r" (value), "r" (addr), "r" (where)
0109                 : "cc");
0110             break;
0111         case 4:
0112             asm volatile("str   %0, [%1, %2]"
0113                 : : "r" (value), "r" (addr), "r" (where)
0114                 : "cc");
0115             break;
0116         }
0117
0118     v = *CSR_PCICMD;
0119     if (v & PCICMD_ABORT) {
0120         *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
0121         return -1;
0122     }
0123
0124     return PCIBIOS_SUCCESSFUL;
0125 }
0126
0127 struct pci_ops dc21285_ops = {
0128     .read   = dc21285_read_config,
0129     .write  = dc21285_write_config,
0130 };
0131
0132 static struct timer_list serr_timer;
0133 static struct timer_list perr_timer;
0134
0135 static void dc21285_enable_error(struct timer_list *timer)
0136 {
0137     del_timer(timer);
0138
0139     if (timer == &serr_timer)
0140         enable_irq(IRQ_PCI_SERR);
0141     else if (timer == &perr_timer)
0142         enable_irq(IRQ_PCI_PERR);
0143 }
0144
0145 /*
0146  * Warn on PCI errors.
0147  */
0148 static irqreturn_t dc21285_abort_irq(int irq, void *dev_id)
0149 {
0150     unsigned int cmd;
0151     unsigned int status;
0152
0153     cmd = *CSR_PCICMD;
0154     status = cmd >> 16;
0155     cmd = cmd & 0xffff;
0156
0157     if (status & PCI_STATUS_REC_MASTER_ABORT) {
0158         printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n",
0159             instruction_pointer(get_irq_regs()));
0160         cmd |= PCI_STATUS_REC_MASTER_ABORT << 16;
0161     }
0162
0163     if (status & PCI_STATUS_REC_TARGET_ABORT) {
0164         printk(KERN_DEBUG "PCI: target abort: ");
0165         pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT |
0166                       PCI_STATUS_SIG_TARGET_ABORT |
0167                       PCI_STATUS_REC_TARGET_ABORT, 1);
0168         printk("\n");
0169
0170         cmd |= PCI_STATUS_REC_TARGET_ABORT << 16;
0171     }
0172
0173     *CSR_PCICMD = cmd;
0174
0175     return IRQ_HANDLED;
0176 }
0177
0178 static irqreturn_t dc21285_serr_irq(int irq, void *dev_id)
0179 {
0180     struct timer_list *timer = dev_id;
0181     unsigned int cntl;
0182
0183     printk(KERN_DEBUG "PCI: system error received: ");
0184     pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
0185     printk("\n");
0186
0187     cntl = *CSR_SA110_CNTL & 0xffffdf07;
0188     *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR;
0189
0190     /*
0191      * back off this interrupt
0192      */
0193     disable_irq(irq);
0194     timer->expires = jiffies + HZ;
0195     add_timer(timer);
0196
0197     return IRQ_HANDLED;
0198 }
0199
0200 static irqreturn_t dc21285_discard_irq(int irq, void *dev_id)
0201 {
0202     printk(KERN_DEBUG "PCI: discard timer expired\n");
0203     *CSR_SA110_CNTL &= 0xffffde07;
0204
0205     return IRQ_HANDLED;
0206 }
0207
0208 static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id)
0209 {
0210     unsigned int cmd;
0211
0212     printk(KERN_DEBUG "PCI: data parity error detected: ");
0213     pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
0214     printk("\n");
0215
0216     cmd = *CSR_PCICMD & 0xffff;
0217     *CSR_PCICMD = cmd | 1 << 24;
0218
0219     return IRQ_HANDLED;
0220 }
0221
0222 static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
0223 {
0224     struct timer_list *timer = dev_id;
0225     unsigned int cmd;
0226
0227     printk(KERN_DEBUG "PCI: parity error detected: ");
0228     pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
0229     printk("\n");
0230
0231     cmd = *CSR_PCICMD & 0xffff;
0232     *CSR_PCICMD = cmd | 1 << 31;
0233
0234     /*
0235      * back off this interrupt
0236      */
0237     disable_irq(irq);
0238     timer->expires = jiffies + HZ;
0239     add_timer(timer);
0240
0241     return IRQ_HANDLED;
0242 }
0243
0244 int __init dc21285_setup(int nr, struct pci_sys_data *sys)
0245 {
0246     struct resource *res;
0247
0248     if (nr || !footbridge_cfn_mode())
0249         return 0;
0250
0251     res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
0252     if (!res) {
0253         printk("out of memory for root bus resources");
0254         return 0;
0255     }
0256
0257     res[0].flags = IORESOURCE_MEM;
0258     res[0].name  = "Footbridge non-prefetch";
0259     res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
0260     res[1].name  = "Footbridge prefetch";
0261
0262     allocate_resource(&iomem_resource, &res[1], 0x20000000,
0263               0xa0000000, 0xffffffff, 0x20000000, NULL, NULL);
0264     allocate_resource(&iomem_resource, &res[0], 0x40000000,
0265               0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
0266
0267     sys->mem_offset  = DC21285_PCI_MEM;
0268
0269     pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
0270     pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
0271
0272     return 1;
0273 }
0274
0275 #define dc21285_request_irq(_a, _b, _c, _d, _e) \
0276     WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
0277
0278 void __init dc21285_preinit(void)
0279 {
0280     unsigned int mem_size, mem_mask;
0281     int cfn_mode;
0282
0283     pcibios_min_mem = 0x81000000;
0284
0285     mem_size = (unsigned int)high_memory - PAGE_OFFSET;
0286     for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
0287         if (mem_mask >= mem_size)
0288             break;
0289
0290     /*
0291      * These registers need to be set up whether we're the
0292      * central function or not.
0293      */
0294     *CSR_SDRAMBASEMASK    = (mem_mask - 1) & 0x0ffc0000;
0295     *CSR_SDRAMBASEOFFSET  = 0;
0296     *CSR_ROMBASEMASK      = 0x80000000;
0297     *CSR_CSRBASEMASK      = 0;
0298     *CSR_CSRBASEOFFSET    = 0;
0299     *CSR_PCIADDR_EXTN     = 0;
0300
0301     cfn_mode = __footbridge_cfn_mode();
0302
0303     printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in "
0304         "%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ?
0305         "central function" : "addin");
0306
0307     if (footbridge_cfn_mode()) {
0308         /*
0309          * Clear any existing errors - we aren't
0310          * interested in historical data...
0311          */
0312         *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) |
0313                   SA110_CNTL_RXSERR;
0314         *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
0315     }
0316
0317     timer_setup(&serr_timer, dc21285_enable_error, 0);
0318     timer_setup(&perr_timer, dc21285_enable_error, 0);
0319
0320     /*
0321      * We don't care if these fail.
0322      */
0323     dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, 0,
0324                 "PCI system error", &serr_timer);
0325     dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, 0,
0326                 "PCI parity error", &perr_timer);
0327     dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, 0,
0328                 "PCI abort", NULL);
0329     dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, 0,
0330                 "Discard timer", NULL);
0331     dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0,
0332                 "PCI data parity", NULL);
0333
0334     if (cfn_mode) {
0335         /*
0336          * Map our SDRAM at a known address in PCI space, just in case
0337          * the firmware had other ideas.  Using a nonzero base is
0338          * necessary, since some VGA cards forcefully use PCI addresses
0339          * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
0340          */
0341         *CSR_PCICSRBASE       = 0xf4000000;
0342         *CSR_PCICSRIOBASE     = 0;
0343         *CSR_PCISDRAMBASE     = __virt_to_bus(PAGE_OFFSET);
0344         *CSR_PCIROMBASE       = 0;
0345         *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
0346                   PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
0347     } else if (footbridge_cfn_mode() != 0) {
0348         /*
0349          * If we are not compiled to accept "add-in" mode, then
0350          * we are using a constant virt_to_bus translation which
0351          * can not hope to cater for the way the host BIOS  has
0352          * set up the machine.
0353          */
0354         panic("PCI: this kernel is compiled for central "
0355             "function mode only");
0356     }
0357 }
0358
0359 void __init dc21285_postinit(void)
0360 {
0361     register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0);
0362 }