arm/mach-footbridge/dc21285-timer.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  linux/arch/arm/mach-footbridge/dc21285-timer.c
0004  *
0005  *  Copyright (C) 1998 Russell King.
0006  *  Copyright (C) 1998 Phil Blundell
0007  */
0008 #include <linux/clockchips.h>
0009 #include <linux/clocksource.h>
0010 #include <linux/init.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/irq.h>
0013 #include <linux/sched_clock.h>
0014
0015 #include <asm/irq.h>
0016
0017 #include <asm/hardware/dec21285.h>
0018 #include <asm/mach/time.h>
0019 #include <asm/system_info.h>
0020
0021 #include "common.h"
0022
0023 static u64 cksrc_dc21285_read(struct clocksource *cs)
0024 {
0025     return cs->mask - *CSR_TIMER2_VALUE;
0026 }
0027
0028 static int cksrc_dc21285_enable(struct clocksource *cs)
0029 {
0030     *CSR_TIMER2_LOAD = cs->mask;
0031     *CSR_TIMER2_CLR = 0;
0032     *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
0033     return 0;
0034 }
0035
0036 static void cksrc_dc21285_disable(struct clocksource *cs)
0037 {
0038     *CSR_TIMER2_CNTL = 0;
0039 }
0040
0041 static struct clocksource cksrc_dc21285 = {
0042     .name       = "dc21285_timer2",
0043     .rating     = 200,
0044     .read       = cksrc_dc21285_read,
0045     .enable     = cksrc_dc21285_enable,
0046     .disable    = cksrc_dc21285_disable,
0047     .mask       = CLOCKSOURCE_MASK(24),
0048     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0049 };
0050
0051 static int ckevt_dc21285_set_next_event(unsigned long delta,
0052     struct clock_event_device *c)
0053 {
0054     *CSR_TIMER1_CLR = 0;
0055     *CSR_TIMER1_LOAD = delta;
0056     *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
0057
0058     return 0;
0059 }
0060
0061 static int ckevt_dc21285_shutdown(struct clock_event_device *c)
0062 {
0063     *CSR_TIMER1_CNTL = 0;
0064     return 0;
0065 }
0066
0067 static int ckevt_dc21285_set_periodic(struct clock_event_device *c)
0068 {
0069     *CSR_TIMER1_CLR = 0;
0070     *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
0071     *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
0072                TIMER_CNTL_DIV16;
0073     return 0;
0074 }
0075
0076 static struct clock_event_device ckevt_dc21285 = {
0077     .name           = "dc21285_timer1",
0078     .features       = CLOCK_EVT_FEAT_PERIODIC |
0079                   CLOCK_EVT_FEAT_ONESHOT,
0080     .rating         = 200,
0081     .irq            = IRQ_TIMER1,
0082     .set_next_event     = ckevt_dc21285_set_next_event,
0083     .set_state_shutdown = ckevt_dc21285_shutdown,
0084     .set_state_periodic = ckevt_dc21285_set_periodic,
0085     .set_state_oneshot  = ckevt_dc21285_shutdown,
0086     .tick_resume        = ckevt_dc21285_set_periodic,
0087 };
0088
0089 static irqreturn_t timer1_interrupt(int irq, void *dev_id)
0090 {
0091     struct clock_event_device *ce = dev_id;
0092
0093     *CSR_TIMER1_CLR = 0;
0094
0095     /* Stop the timer if in one-shot mode */
0096     if (clockevent_state_oneshot(ce))
0097         *CSR_TIMER1_CNTL = 0;
0098
0099     ce->event_handler(ce);
0100
0101     return IRQ_HANDLED;
0102 }
0103
0104 /*
0105  * Set up timer interrupt.
0106  */
0107 void __init footbridge_timer_init(void)
0108 {
0109     struct clock_event_device *ce = &ckevt_dc21285;
0110     unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
0111
0112     clocksource_register_hz(&cksrc_dc21285, rate);
0113
0114     if (request_irq(ce->irq, timer1_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
0115             "dc21285_timer1", &ckevt_dc21285))
0116         pr_err("Failed to request irq %d (dc21285_timer1)", ce->irq);
0117
0118     ce->cpumask = cpumask_of(smp_processor_id());
0119     clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
0120 }
0121
0122 static u64 notrace footbridge_read_sched_clock(void)
0123 {
0124     return ~*CSR_TIMER3_VALUE;
0125 }
0126
0127 void __init footbridge_sched_clock(void)
0128 {
0129     unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
0130
0131     *CSR_TIMER3_LOAD = 0;
0132     *CSR_TIMER3_CLR = 0;
0133     *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
0134
0135     sched_clock_register(footbridge_read_sched_clock, 24, rate);
0136 }