arm/mach-exynos/sleep.S

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0004  *      http://www.samsung.com
0005  *
0006  * Exynos low-level resume code
0007  */
0008
0009 #include <linux/linkage.h>
0010 #include <asm/asm-offsets.h>
0011 #include <asm/hardware/cache-l2x0.h>
0012 #include "smc.h"
0013
0014 #define CPU_MASK    0xff0ffff0
0015 #define CPU_CORTEX_A9   0x410fc090
0016
0017     .text
0018     .align
0019
0020     /*
0021      * sleep magic, to allow the bootloader to check for an valid
0022      * image to resume to. Must be the first word before the
0023      * exynos_cpu_resume entry.
0024      */
0025
0026     .word   0x2bedf00d
0027
0028     /*
0029      * exynos_cpu_resume
0030      *
0031      * resume code entry for bootloader to call
0032      */
0033
0034 ENTRY(exynos_cpu_resume)
0035 #ifdef CONFIG_CACHE_L2X0
0036     mrc p15, 0, r0, c0, c0, 0
0037     ldr r1, =CPU_MASK
0038     and r0, r0, r1
0039     ldr r1, =CPU_CORTEX_A9
0040     cmp r0, r1
0041     bleq    l2c310_early_resume
0042 #endif
0043     b   cpu_resume
0044 ENDPROC(exynos_cpu_resume)
0045
0046     .align
0047     .arch armv7-a
0048     .arch_extension sec
0049 ENTRY(exynos_cpu_resume_ns)
0050     mrc p15, 0, r0, c0, c0, 0
0051     ldr r1, =CPU_MASK
0052     and r0, r0, r1
0053     ldr r1, =CPU_CORTEX_A9
0054     cmp r0, r1
0055     bne skip_cp15
0056
0057     adr r0, _cp15_save_power
0058     ldr r1, [r0]
0059     ldr r1, [r0, r1]
0060     adr r0, _cp15_save_diag
0061     ldr r2, [r0]
0062     ldr r2, [r0, r2]
0063     mov r0, #SMC_CMD_C15RESUME
0064     dsb
0065     smc #0
0066 #ifdef CONFIG_CACHE_L2X0
0067     adr r0, 1f
0068     ldr r2, [r0]
0069     add r0, r2, r0
0070
0071     /* Check that the address has been initialised. */
0072     ldr r1, [r0, #L2X0_R_PHY_BASE]
0073     teq r1, #0
0074     beq skip_l2x0
0075
0076     /* Check if controller has been enabled. */
0077     ldr r2, [r1, #L2X0_CTRL]
0078     tst r2, #0x1
0079     bne skip_l2x0
0080
0081     ldr r1, [r0, #L2X0_R_TAG_LATENCY]
0082     ldr r2, [r0, #L2X0_R_DATA_LATENCY]
0083     ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
0084     mov r0, #SMC_CMD_L2X0SETUP1
0085     smc #0
0086
0087     /* Reload saved regs pointer because smc corrupts registers. */
0088     adr r0, 1f
0089     ldr r2, [r0]
0090     add r0, r2, r0
0091
0092     ldr r1, [r0, #L2X0_R_PWR_CTRL]
0093     ldr r2, [r0, #L2X0_R_AUX_CTRL]
0094     mov r0, #SMC_CMD_L2X0SETUP2
0095     smc #0
0096
0097     mov r0, #SMC_CMD_L2X0INVALL
0098     smc #0
0099
0100     mov r1, #1
0101     mov r0, #SMC_CMD_L2X0CTRL
0102     smc #0
0103 skip_l2x0:
0104 #endif /* CONFIG_CACHE_L2X0 */
0105 skip_cp15:
0106     b   cpu_resume
0107 ENDPROC(exynos_cpu_resume_ns)
0108
0109     .align
0110 _cp15_save_power:
0111     .long   cp15_save_power - .
0112 _cp15_save_diag:
0113     .long   cp15_save_diag - .
0114 #ifdef CONFIG_CACHE_L2X0
0115 1:  .long   l2x0_saved_regs - .
0116 #endif /* CONFIG_CACHE_L2X0 */
0117
0118     .data
0119     .align  2
0120     .globl cp15_save_diag
0121 cp15_save_diag:
0122     .long   0   @ cp15 diagnostic
0123     .globl cp15_save_power
0124 cp15_save_power:
0125     .long   0   @ cp15 power control