arm/mach-exynos/mcpm-exynos.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2014 Samsung Electronics Co., Ltd.
0003 //      http://www.samsung.com
0004 //
0005 // Based on arch/arm/mach-vexpress/dcscb.c
0006
0007 #include <linux/arm-cci.h>
0008 #include <linux/delay.h>
0009 #include <linux/io.h>
0010 #include <linux/of_address.h>
0011 #include <linux/syscore_ops.h>
0012 #include <linux/soc/samsung/exynos-regs-pmu.h>
0013
0014 #include <asm/cputype.h>
0015 #include <asm/cp15.h>
0016 #include <asm/mcpm.h>
0017 #include <asm/smp_plat.h>
0018
0019 #include "common.h"
0020
0021 #define EXYNOS5420_CPUS_PER_CLUSTER 4
0022 #define EXYNOS5420_NR_CLUSTERS      2
0023
0024 #define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN   BIT(9)
0025 #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE  BIT(29)
0026 #define EXYNOS5420_USE_L2_COMMON_UP_STATE   BIT(30)
0027
0028 static void __iomem *ns_sram_base_addr __ro_after_init;
0029 static bool secure_firmware __ro_after_init;
0030
0031 /*
0032  * The common v7_exit_coherency_flush API could not be used because of the
0033  * Erratum 799270 workaround. This macro is the same as the common one (in
0034  * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
0035  */
0036 #define exynos_v7_exit_coherency_flush(level) \
0037     asm volatile( \
0038     "mrc    p15, 0, r0, c1, c0, 0   @ get SCTLR\n\t" \
0039     "bic    r0, r0, #"__stringify(CR_C)"\n\t" \
0040     "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR\n\t" \
0041     "isb\n\t"\
0042     "bl v7_flush_dcache_"__stringify(level)"\n\t" \
0043     "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR\n\t" \
0044     "bic    r0, r0, #(1 << 6)   @ disable local coherency\n\t" \
0045     /* Dummy Load of a device register to avoid Erratum 799270 */ \
0046     "ldr    r4, [%0]\n\t" \
0047     "and    r4, r4, #0\n\t" \
0048     "orr    r0, r0, r4\n\t" \
0049     "mcr    p15, 0, r0, c1, c0, 1   @ set ACTLR\n\t" \
0050     "isb\n\t" \
0051     "dsb\n\t" \
0052     : \
0053     : "Ir" (pmu_base_addr + S5P_INFORM0) \
0054     : "r0", "r1", "r2", "r3", "r4", "r5", "r6", \
0055       "r9", "r10", "ip", "lr", "memory")
0056
0057 static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
0058 {
0059     unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
0060     bool state;
0061
0062     pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
0063     if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
0064         cluster >= EXYNOS5420_NR_CLUSTERS)
0065         return -EINVAL;
0066
0067     state = exynos_cpu_power_state(cpunr);
0068     exynos_cpu_power_up(cpunr);
0069     if (!state && secure_firmware) {
0070         /*
0071          * This assumes the cluster number of the big cores(Cortex A15)
0072          * is 0 and the Little cores(Cortex A7) is 1.
0073          * When the system was booted from the Little core,
0074          * they should be reset during power up cpu.
0075          */
0076         if (cluster &&
0077             cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
0078             unsigned int timeout = 16;
0079
0080             /*
0081              * Before we reset the Little cores, we should wait
0082              * the SPARE2 register is set to 1 because the init
0083              * codes of the iROM will set the register after
0084              * initialization.
0085              */
0086             while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
0087                 timeout--;
0088                 udelay(10);
0089             }
0090
0091             if (timeout == 0) {
0092                 pr_err("cpu %u cluster %u powerup failed\n",
0093                        cpu, cluster);
0094                 exynos_cpu_power_down(cpunr);
0095                 return -ETIMEDOUT;
0096             }
0097
0098             pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
0099                     EXYNOS_SWRESET);
0100         }
0101     }
0102
0103     return 0;
0104 }
0105
0106 static int exynos_cluster_powerup(unsigned int cluster)
0107 {
0108     pr_debug("%s: cluster %u\n", __func__, cluster);
0109     if (cluster >= EXYNOS5420_NR_CLUSTERS)
0110         return -EINVAL;
0111
0112     exynos_cluster_power_up(cluster);
0113     return 0;
0114 }
0115
0116 static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
0117 {
0118     unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
0119
0120     pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
0121     BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
0122             cluster >= EXYNOS5420_NR_CLUSTERS);
0123     exynos_cpu_power_down(cpunr);
0124 }
0125
0126 static void exynos_cluster_powerdown_prepare(unsigned int cluster)
0127 {
0128     pr_debug("%s: cluster %u\n", __func__, cluster);
0129     BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS);
0130     exynos_cluster_power_down(cluster);
0131 }
0132
0133 static void exynos_cpu_cache_disable(void)
0134 {
0135     /* Disable and flush the local CPU cache. */
0136     exynos_v7_exit_coherency_flush(louis);
0137 }
0138
0139 static void exynos_cluster_cache_disable(void)
0140 {
0141     if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
0142         /*
0143          * On the Cortex-A15 we need to disable
0144          * L2 prefetching before flushing the cache.
0145          */
0146         asm volatile(
0147         "mcr    p15, 1, %0, c15, c0, 3\n\t"
0148         "isb\n\t"
0149         "dsb"
0150         : : "r" (0x400));
0151     }
0152
0153     /* Flush all cache levels for this cluster. */
0154     exynos_v7_exit_coherency_flush(all);
0155
0156     /*
0157      * Disable cluster-level coherency by masking
0158      * incoming snoops and DVM messages:
0159      */
0160     cci_disable_port_by_cpu(read_cpuid_mpidr());
0161 }
0162
0163 static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
0164 {
0165     unsigned int tries = 100;
0166     unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
0167
0168     pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
0169     BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
0170             cluster >= EXYNOS5420_NR_CLUSTERS);
0171
0172     /* Wait for the core state to be OFF */
0173     while (tries--) {
0174         if ((exynos_cpu_power_state(cpunr) == 0))
0175             return 0; /* success: the CPU is halted */
0176
0177         /* Otherwise, wait and retry: */
0178         msleep(1);
0179     }
0180
0181     return -ETIMEDOUT; /* timeout */
0182 }
0183
0184 static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster)
0185 {
0186     /* especially when resuming: make sure power control is set */
0187     exynos_cpu_powerup(cpu, cluster);
0188 }
0189
0190 static const struct mcpm_platform_ops exynos_power_ops = {
0191     .cpu_powerup        = exynos_cpu_powerup,
0192     .cluster_powerup    = exynos_cluster_powerup,
0193     .cpu_powerdown_prepare  = exynos_cpu_powerdown_prepare,
0194     .cluster_powerdown_prepare = exynos_cluster_powerdown_prepare,
0195     .cpu_cache_disable  = exynos_cpu_cache_disable,
0196     .cluster_cache_disable  = exynos_cluster_cache_disable,
0197     .wait_for_powerdown = exynos_wait_for_powerdown,
0198     .cpu_is_up      = exynos_cpu_is_up,
0199 };
0200
0201 /*
0202  * Enable cluster-level coherency, in preparation for turning on the MMU.
0203  */
0204 static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
0205 {
0206     asm volatile ("\n"
0207     "cmp    r0, #1\n"
0208     "bxne   lr\n"
0209     "b  cci_enable_port_for_self");
0210 }
0211
0212 static const struct of_device_id exynos_dt_mcpm_match[] = {
0213     { .compatible = "samsung,exynos5420" },
0214     { .compatible = "samsung,exynos5800" },
0215     {},
0216 };
0217
0218 static void exynos_mcpm_setup_entry_point(void)
0219 {
0220     /*
0221      * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
0222      * as part of secondary_cpu_start().  Let's redirect it to the
0223      * mcpm_entry_point(). This is done during both secondary boot-up as
0224      * well as system resume.
0225      */
0226     __raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
0227     __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
0228     __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
0229 }
0230
0231 static struct syscore_ops exynos_mcpm_syscore_ops = {
0232     .resume = exynos_mcpm_setup_entry_point,
0233 };
0234
0235 static int __init exynos_mcpm_init(void)
0236 {
0237     struct device_node *node;
0238     unsigned int value, i;
0239     int ret;
0240
0241     node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
0242     if (!node)
0243         return -ENODEV;
0244     of_node_put(node);
0245
0246     if (!cci_probed())
0247         return -ENODEV;
0248
0249     node = of_find_compatible_node(NULL, NULL,
0250             "samsung,exynos4210-sysram-ns");
0251     if (!node)
0252         return -ENODEV;
0253
0254     ns_sram_base_addr = of_iomap(node, 0);
0255     of_node_put(node);
0256     if (!ns_sram_base_addr) {
0257         pr_err("failed to map non-secure iRAM base address\n");
0258         return -ENOMEM;
0259     }
0260
0261     secure_firmware = exynos_secure_firmware_available();
0262
0263     /*
0264      * To increase the stability of KFC reset we need to program
0265      * the PMU SPARE3 register
0266      */
0267     pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
0268
0269     ret = mcpm_platform_register(&exynos_power_ops);
0270     if (!ret)
0271         ret = mcpm_sync_init(exynos_pm_power_up_setup);
0272     if (!ret)
0273         ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */
0274     if (ret) {
0275         iounmap(ns_sram_base_addr);
0276         return ret;
0277     }
0278
0279     mcpm_smp_set_ops();
0280
0281     pr_info("Exynos MCPM support installed\n");
0282
0283     /*
0284      * On Exynos5420/5800 for the A15 and A7 clusters:
0285      *
0286      * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
0287      * in a cluster are turned off before turning off the cluster L2.
0288      *
0289      * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
0290      * off before waking it up.
0291      *
0292      * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
0293      * turned on before the first man is powered up.
0294      */
0295     for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
0296         value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
0297         value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
0298              EXYNOS5420_USE_ARM_CORE_DOWN_STATE    |
0299              EXYNOS5420_USE_L2_COMMON_UP_STATE;
0300         pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
0301     }
0302
0303     exynos_mcpm_setup_entry_point();
0304
0305     register_syscore_ops(&exynos_mcpm_syscore_ops);
0306
0307     return ret;
0308 }
0309
0310 early_initcall(exynos_mcpm_init);