arm/mach-exynos/common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
0004  *      http://www.samsung.com
0005  *
0006  * Common Header for Exynos machines
0007  */
0008
0009 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
0010 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
0011
0012 #include <linux/platform_data/cpuidle-exynos.h>
0013
0014 #define EXYNOS3250_SOC_ID   0xE3472000
0015 #define EXYNOS3_SOC_MASK    0xFFFFF000
0016
0017 #define EXYNOS4210_CPU_ID   0x43210000
0018 #define EXYNOS4412_CPU_ID   0xE4412200
0019 #define EXYNOS4_CPU_MASK    0xFFFE0000
0020
0021 #define EXYNOS5250_SOC_ID   0x43520000
0022 #define EXYNOS5410_SOC_ID   0xE5410000
0023 #define EXYNOS5420_SOC_ID   0xE5420000
0024 #define EXYNOS5800_SOC_ID   0xE5422000
0025 #define EXYNOS5_SOC_MASK    0xFFFFF000
0026
0027 extern unsigned long exynos_cpu_id;
0028
0029 #define IS_SAMSUNG_CPU(name, id, mask)      \
0030 static inline int is_samsung_##name(void)   \
0031 {                       \
0032     return ((exynos_cpu_id & mask) == (id & mask)); \
0033 }
0034
0035 IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
0036 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
0037 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
0038 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
0039 IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
0040 IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
0041 IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
0042
0043 #if defined(CONFIG_SOC_EXYNOS3250)
0044 # define soc_is_exynos3250()    is_samsung_exynos3250()
0045 #else
0046 # define soc_is_exynos3250()    0
0047 #endif
0048
0049 #if defined(CONFIG_CPU_EXYNOS4210)
0050 # define soc_is_exynos4210()    is_samsung_exynos4210()
0051 #else
0052 # define soc_is_exynos4210()    0
0053 #endif
0054
0055 #if defined(CONFIG_SOC_EXYNOS4412)
0056 # define soc_is_exynos4412()    is_samsung_exynos4412()
0057 #else
0058 # define soc_is_exynos4412()    0
0059 #endif
0060
0061 #define EXYNOS4210_REV_0    (0x0)
0062 #define EXYNOS4210_REV_1_0  (0x10)
0063 #define EXYNOS4210_REV_1_1  (0x11)
0064
0065 #if defined(CONFIG_SOC_EXYNOS5250)
0066 # define soc_is_exynos5250()    is_samsung_exynos5250()
0067 #else
0068 # define soc_is_exynos5250()    0
0069 #endif
0070
0071 #if defined(CONFIG_SOC_EXYNOS5410)
0072 # define soc_is_exynos5410()    is_samsung_exynos5410()
0073 #else
0074 # define soc_is_exynos5410()    0
0075 #endif
0076
0077 #if defined(CONFIG_SOC_EXYNOS5420)
0078 # define soc_is_exynos5420()    is_samsung_exynos5420()
0079 #else
0080 # define soc_is_exynos5420()    0
0081 #endif
0082
0083 #if defined(CONFIG_SOC_EXYNOS5800)
0084 # define soc_is_exynos5800()    is_samsung_exynos5800()
0085 #else
0086 # define soc_is_exynos5800()    0
0087 #endif
0088
0089 extern u32 cp15_save_diag;
0090 extern u32 cp15_save_power;
0091
0092 extern void __iomem *sysram_ns_base_addr;
0093 extern void __iomem *sysram_base_addr;
0094 extern phys_addr_t sysram_base_phys;
0095 extern void __iomem *pmu_base_addr;
0096 void exynos_sysram_init(void);
0097
0098 enum {
0099     FW_DO_IDLE_SLEEP,
0100     FW_DO_IDLE_AFTR,
0101 };
0102
0103 void exynos_firmware_init(void);
0104
0105 /* CPU BOOT mode flag for Exynos3250 SoC bootloader */
0106 #define C2_STATE    (1 << 3)
0107 /*
0108  * Magic values for bootloader indicating chosen low power mode.
0109  * See also Documentation/arm/samsung/bootloader-interface.rst
0110  */
0111 #define EXYNOS_SLEEP_MAGIC  0x00000bad
0112 #define EXYNOS_AFTR_MAGIC   0xfcba0d10
0113
0114 bool __init exynos_secure_firmware_available(void);
0115 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
0116 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
0117
0118 #ifdef CONFIG_PM_SLEEP
0119 extern void __init exynos_pm_init(void);
0120 #else
0121 static inline void exynos_pm_init(void) {}
0122 #endif
0123
0124 extern void exynos_cpu_resume(void);
0125 extern void exynos_cpu_resume_ns(void);
0126
0127 extern const struct smp_operations exynos_smp_ops;
0128
0129 extern void exynos_cpu_power_down(int cpu);
0130 extern void exynos_cpu_power_up(int cpu);
0131 extern int  exynos_cpu_power_state(int cpu);
0132 extern void exynos_cluster_power_down(int cluster);
0133 extern void exynos_cluster_power_up(int cluster);
0134 extern int  exynos_cluster_power_state(int cluster);
0135 extern void exynos_cpu_save_register(void);
0136 extern void exynos_cpu_restore_register(void);
0137 extern void exynos_pm_central_suspend(void);
0138 extern int exynos_pm_central_resume(void);
0139 extern void exynos_enter_aftr(void);
0140 #ifdef CONFIG_SMP
0141 extern void exynos_scu_enable(void);
0142 #else
0143 static inline void exynos_scu_enable(void) { }
0144 #endif
0145
0146 extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
0147
0148 extern void exynos_set_delayed_reset_assertion(bool enable);
0149
0150 extern unsigned int exynos_rev(void);
0151 extern void exynos_core_restart(u32 core_id);
0152 extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
0153 extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
0154
0155 static inline void pmu_raw_writel(u32 val, u32 offset)
0156 {
0157     writel_relaxed(val, pmu_base_addr + offset);
0158 }
0159
0160 static inline u32 pmu_raw_readl(u32 offset)
0161 {
0162     return readl_relaxed(pmu_base_addr + offset);
0163 }
0164
0165 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */