arm/mach-ep93xx/timer-ep93xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/kernel.h>
0003 #include <linux/init.h>
0004 #include <linux/clocksource.h>
0005 #include <linux/clockchips.h>
0006 #include <linux/sched_clock.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/irq.h>
0009 #include <linux/io.h>
0010 #include <asm/mach/time.h>
0011 #include "soc.h"
0012
0013 /*************************************************************************
0014  * Timer handling for EP93xx
0015  *************************************************************************
0016  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
0017  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
0018  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
0019  * is free-running, and can't generate interrupts.
0020  *
0021  * The 508 kHz timers are ideal for use for the timer interrupt, as the
0022  * most common values of HZ divide 508 kHz nicely.  We pick the 32 bit
0023  * timer (timer 3) to get as long sleep intervals as possible when using
0024  * CONFIG_NO_HZ.
0025  *
0026  * The higher clock rate of timer 4 makes it a better choice than the
0027  * other timers for use as clock source and for sched_clock(), providing
0028  * a stable 40 bit time base.
0029  *************************************************************************
0030  */
0031 #define EP93XX_TIMER_REG(x)     (EP93XX_TIMER_BASE + (x))
0032 #define EP93XX_TIMER1_LOAD      EP93XX_TIMER_REG(0x00)
0033 #define EP93XX_TIMER1_VALUE     EP93XX_TIMER_REG(0x04)
0034 #define EP93XX_TIMER1_CONTROL       EP93XX_TIMER_REG(0x08)
0035 #define EP93XX_TIMER123_CONTROL_ENABLE  (1 << 7)
0036 #define EP93XX_TIMER123_CONTROL_MODE    (1 << 6)
0037 #define EP93XX_TIMER123_CONTROL_CLKSEL  (1 << 3)
0038 #define EP93XX_TIMER1_CLEAR     EP93XX_TIMER_REG(0x0c)
0039 #define EP93XX_TIMER2_LOAD      EP93XX_TIMER_REG(0x20)
0040 #define EP93XX_TIMER2_VALUE     EP93XX_TIMER_REG(0x24)
0041 #define EP93XX_TIMER2_CONTROL       EP93XX_TIMER_REG(0x28)
0042 #define EP93XX_TIMER2_CLEAR     EP93XX_TIMER_REG(0x2c)
0043 #define EP93XX_TIMER4_VALUE_LOW     EP93XX_TIMER_REG(0x60)
0044 #define EP93XX_TIMER4_VALUE_HIGH    EP93XX_TIMER_REG(0x64)
0045 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
0046 #define EP93XX_TIMER3_LOAD      EP93XX_TIMER_REG(0x80)
0047 #define EP93XX_TIMER3_VALUE     EP93XX_TIMER_REG(0x84)
0048 #define EP93XX_TIMER3_CONTROL       EP93XX_TIMER_REG(0x88)
0049 #define EP93XX_TIMER3_CLEAR     EP93XX_TIMER_REG(0x8c)
0050
0051 #define EP93XX_TIMER123_RATE        508469
0052 #define EP93XX_TIMER4_RATE      983040
0053
0054 static u64 notrace ep93xx_read_sched_clock(void)
0055 {
0056     u64 ret;
0057
0058     ret = readl(EP93XX_TIMER4_VALUE_LOW);
0059     ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
0060     return ret;
0061 }
0062
0063 u64 ep93xx_clocksource_read(struct clocksource *c)
0064 {
0065     u64 ret;
0066
0067     ret = readl(EP93XX_TIMER4_VALUE_LOW);
0068     ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
0069     return (u64) ret;
0070 }
0071
0072 static int ep93xx_clkevt_set_next_event(unsigned long next,
0073                     struct clock_event_device *evt)
0074 {
0075     /* Default mode: periodic, off, 508 kHz */
0076     u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
0077             EP93XX_TIMER123_CONTROL_CLKSEL;
0078
0079     /* Clear timer */
0080     writel(tmode, EP93XX_TIMER3_CONTROL);
0081
0082     /* Set next event */
0083     writel(next, EP93XX_TIMER3_LOAD);
0084     writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
0085            EP93XX_TIMER3_CONTROL);
0086         return 0;
0087 }
0088
0089
0090 static int ep93xx_clkevt_shutdown(struct clock_event_device *evt)
0091 {
0092     /* Disable timer */
0093     writel(0, EP93XX_TIMER3_CONTROL);
0094
0095     return 0;
0096 }
0097
0098 static struct clock_event_device ep93xx_clockevent = {
0099     .name           = "timer1",
0100     .features       = CLOCK_EVT_FEAT_ONESHOT,
0101     .set_state_shutdown = ep93xx_clkevt_shutdown,
0102     .set_state_oneshot  = ep93xx_clkevt_shutdown,
0103     .tick_resume        = ep93xx_clkevt_shutdown,
0104     .set_next_event     = ep93xx_clkevt_set_next_event,
0105     .rating         = 300,
0106 };
0107
0108 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
0109 {
0110     struct clock_event_device *evt = dev_id;
0111
0112     /* Writing any value clears the timer interrupt */
0113     writel(1, EP93XX_TIMER3_CLEAR);
0114
0115     evt->event_handler(evt);
0116
0117     return IRQ_HANDLED;
0118 }
0119
0120 void __init ep93xx_timer_init(void)
0121 {
0122     int irq = IRQ_EP93XX_TIMER3;
0123     unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL;
0124
0125     /* Enable and register clocksource and sched_clock on timer 4 */
0126     writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
0127            EP93XX_TIMER4_VALUE_HIGH);
0128     clocksource_mmio_init(NULL, "timer4",
0129                   EP93XX_TIMER4_RATE, 200, 40,
0130                   ep93xx_clocksource_read);
0131     sched_clock_register(ep93xx_read_sched_clock, 40,
0132                  EP93XX_TIMER4_RATE);
0133
0134     /* Set up clockevent on timer 3 */
0135     if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer",
0136             &ep93xx_clockevent))
0137         pr_err("Failed to request irq %d (ep93xx timer)\n", irq);
0138     clockevents_config_and_register(&ep93xx_clockevent,
0139                     EP93XX_TIMER123_RATE,
0140                     1,
0141                     0xffffffffU);
0142 }