arm/mach-ep93xx/dma.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * arch/arm/mach-ep93xx/dma.c
0004  *
0005  * Platform support code for the EP93xx dmaengine driver.
0006  *
0007  * Copyright (C) 2011 Mika Westerberg
0008  *
0009  * This work is based on the original dma-m2p implementation with
0010  * following copyrights:
0011  *
0012  *   Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
0013  *   Copyright (C) 2006 Applied Data Systems
0014  *   Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
0015  */
0016
0017 #include <linux/dmaengine.h>
0018 #include <linux/dma-mapping.h>
0019 #include <linux/init.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/kernel.h>
0022 #include <linux/platform_device.h>
0023
0024 #include <linux/platform_data/dma-ep93xx.h>
0025 #include "hardware.h"
0026
0027 #include "soc.h"
0028
0029 #define DMA_CHANNEL(_name, _base, _irq) \
0030     { .name = (_name), .base = (_base), .irq = (_irq) }
0031
0032 /*
0033  * DMA M2P channels.
0034  *
0035  * On the EP93xx chip the following peripherals my be allocated to the 10
0036  * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
0037  *
0038  *  I2S contains 3 Tx and 3 Rx DMA Channels
0039  *  AAC contains 3 Tx and 3 Rx DMA Channels
0040  *  UART1   contains 1 Tx and 1 Rx DMA Channels
0041  *  UART2   contains 1 Tx and 1 Rx DMA Channels
0042  *  UART3   contains 1 Tx and 1 Rx DMA Channels
0043  *  IrDA    contains 1 Tx and 1 Rx DMA Channels
0044  *
0045  * Registers are mapped statically in ep93xx_map_io().
0046  */
0047 static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
0048     DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
0049     DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
0050     DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
0051     DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
0052     DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
0053     DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
0054     DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
0055     DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
0056     DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
0057     DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
0058 };
0059
0060 static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
0061     .channels       = ep93xx_dma_m2p_channels,
0062     .num_channels       = ARRAY_SIZE(ep93xx_dma_m2p_channels),
0063 };
0064
0065 static u64 ep93xx_dma_m2p_mask = DMA_BIT_MASK(32);
0066
0067 static struct platform_device ep93xx_dma_m2p_device = {
0068     .name           = "ep93xx-dma-m2p",
0069     .id         = -1,
0070     .dev            = {
0071         .platform_data      = &ep93xx_dma_m2p_data,
0072         .dma_mask       = &ep93xx_dma_m2p_mask,
0073         .coherent_dma_mask  = DMA_BIT_MASK(32),
0074     },
0075 };
0076
0077 /*
0078  * DMA M2M channels.
0079  *
0080  * There are 2 M2M channels which support memcpy/memset and in addition simple
0081  * hardware requests from/to SSP and IDE. We do not implement an external
0082  * hardware requests.
0083  *
0084  * Registers are mapped statically in ep93xx_map_io().
0085  */
0086 static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
0087     DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
0088     DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
0089 };
0090
0091 static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
0092     .channels       = ep93xx_dma_m2m_channels,
0093     .num_channels       = ARRAY_SIZE(ep93xx_dma_m2m_channels),
0094 };
0095
0096 static u64 ep93xx_dma_m2m_mask = DMA_BIT_MASK(32);
0097
0098 static struct platform_device ep93xx_dma_m2m_device = {
0099     .name           = "ep93xx-dma-m2m",
0100     .id         = -1,
0101     .dev            = {
0102         .platform_data      = &ep93xx_dma_m2m_data,
0103         .dma_mask       = &ep93xx_dma_m2m_mask,
0104         .coherent_dma_mask  = DMA_BIT_MASK(32),
0105     },
0106 };
0107
0108 static int __init ep93xx_dma_init(void)
0109 {
0110     platform_device_register(&ep93xx_dma_m2p_device);
0111     platform_device_register(&ep93xx_dma_m2m_device);
0112     return 0;
0113 }
0114 arch_initcall(ep93xx_dma_init);