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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * arch/arm/mach-ep93xx/clock.c
0004  * Clock control for Cirrus EP93xx chips.
0005  *
0006  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
0007  */
0008 
0009 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/clk.h>
0013 #include <linux/err.h>
0014 #include <linux/module.h>
0015 #include <linux/string.h>
0016 #include <linux/io.h>
0017 #include <linux/spinlock.h>
0018 #include <linux/clkdev.h>
0019 #include <linux/clk-provider.h>
0020 #include <linux/soc/cirrus/ep93xx.h>
0021 
0022 #include "hardware.h"
0023 
0024 #include <asm/div64.h>
0025 
0026 #include "soc.h"
0027 
0028 static DEFINE_SPINLOCK(clk_lock);
0029 
0030 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
0031 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
0032 static char pclk_divisors[] = { 1, 2, 4, 8 };
0033 
0034 static char adc_divisors[] = { 16, 4 };
0035 static char sclk_divisors[] = { 2, 4 };
0036 static char lrclk_divisors[] = { 32, 64, 128 };
0037 
0038 static const char * const mux_parents[] = {
0039     "xtali",
0040     "pll1",
0041     "pll2"
0042 };
0043 
0044 /*
0045  * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
0046  */
0047 static unsigned long calc_pll_rate(unsigned long long rate, u32 config_word)
0048 {
0049     int i;
0050 
0051     rate *= ((config_word >> 11) & 0x1f) + 1;       /* X1FBD */
0052     rate *= ((config_word >> 5) & 0x3f) + 1;        /* X2FBD */
0053     do_div(rate, (config_word & 0x1f) + 1);         /* X2IPD */
0054     for (i = 0; i < ((config_word >> 16) & 3); i++)     /* PS */
0055         rate >>= 1;
0056 
0057     return (unsigned long)rate;
0058 }
0059 
0060 struct clk_psc {
0061     struct clk_hw hw;
0062     void __iomem *reg;
0063     u8 bit_idx;
0064     u32 mask;
0065     u8 shift;
0066     u8 width;
0067     char *div;
0068     u8 num_div;
0069     spinlock_t *lock;
0070 };
0071 
0072 #define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw)
0073 
0074 static int ep93xx_clk_is_enabled(struct clk_hw *hw)
0075 {
0076     struct clk_psc *psc = to_clk_psc(hw);
0077     u32 val = readl(psc->reg);
0078 
0079     return (val & BIT(psc->bit_idx)) ? 1 : 0;
0080 }
0081 
0082 static int ep93xx_clk_enable(struct clk_hw *hw)
0083 {
0084     struct clk_psc *psc = to_clk_psc(hw);
0085     unsigned long flags = 0;
0086     u32 val;
0087 
0088     if (psc->lock)
0089         spin_lock_irqsave(psc->lock, flags);
0090 
0091     val = __raw_readl(psc->reg);
0092     val |= BIT(psc->bit_idx);
0093 
0094     ep93xx_syscon_swlocked_write(val, psc->reg);
0095 
0096     if (psc->lock)
0097         spin_unlock_irqrestore(psc->lock, flags);
0098 
0099     return 0;
0100 }
0101 
0102 static void ep93xx_clk_disable(struct clk_hw *hw)
0103 {
0104     struct clk_psc *psc = to_clk_psc(hw);
0105     unsigned long flags = 0;
0106     u32 val;
0107 
0108     if (psc->lock)
0109         spin_lock_irqsave(psc->lock, flags);
0110 
0111     val = __raw_readl(psc->reg);
0112     val &= ~BIT(psc->bit_idx);
0113 
0114     ep93xx_syscon_swlocked_write(val, psc->reg);
0115 
0116     if (psc->lock)
0117         spin_unlock_irqrestore(psc->lock, flags);
0118 }
0119 
0120 static const struct clk_ops clk_ep93xx_gate_ops = {
0121     .enable = ep93xx_clk_enable,
0122     .disable = ep93xx_clk_disable,
0123     .is_enabled = ep93xx_clk_is_enabled,
0124 };
0125 
0126 static struct clk_hw *ep93xx_clk_register_gate(const char *name,
0127                     const char *parent_name,
0128                     void __iomem *reg,
0129                     u8 bit_idx)
0130 {
0131     struct clk_init_data init;
0132     struct clk_psc *psc;
0133     struct clk *clk;
0134 
0135     psc = kzalloc(sizeof(*psc), GFP_KERNEL);
0136     if (!psc)
0137         return ERR_PTR(-ENOMEM);
0138 
0139     init.name = name;
0140     init.ops = &clk_ep93xx_gate_ops;
0141     init.flags = CLK_SET_RATE_PARENT;
0142     init.parent_names = (parent_name ? &parent_name : NULL);
0143     init.num_parents = (parent_name ? 1 : 0);
0144 
0145     psc->reg = reg;
0146     psc->bit_idx = bit_idx;
0147     psc->hw.init = &init;
0148     psc->lock = &clk_lock;
0149 
0150     clk = clk_register(NULL, &psc->hw);
0151     if (IS_ERR(clk)) {
0152         kfree(psc);
0153         return ERR_CAST(clk);
0154     }
0155 
0156     return &psc->hw;
0157 }
0158 
0159 static u8 ep93xx_mux_get_parent(struct clk_hw *hw)
0160 {
0161     struct clk_psc *psc = to_clk_psc(hw);
0162     u32 val = __raw_readl(psc->reg);
0163 
0164     if (!(val & EP93XX_SYSCON_CLKDIV_ESEL))
0165         return 0;
0166 
0167     if (!(val & EP93XX_SYSCON_CLKDIV_PSEL))
0168         return 1;
0169 
0170     return 2;
0171 }
0172 
0173 static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index)
0174 {
0175     struct clk_psc *psc = to_clk_psc(hw);
0176     unsigned long flags = 0;
0177     u32 val;
0178 
0179     if (index >= ARRAY_SIZE(mux_parents))
0180         return -EINVAL;
0181 
0182     if (psc->lock)
0183         spin_lock_irqsave(psc->lock, flags);
0184 
0185     val = __raw_readl(psc->reg);
0186     val &= ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL);
0187 
0188 
0189     if (index != 0) {
0190         val |= EP93XX_SYSCON_CLKDIV_ESEL;
0191         val |= (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0;
0192     }
0193 
0194     ep93xx_syscon_swlocked_write(val, psc->reg);
0195 
0196     if (psc->lock)
0197         spin_unlock_irqrestore(psc->lock, flags);
0198 
0199     return 0;
0200 }
0201 
0202 static bool is_best(unsigned long rate, unsigned long now,
0203              unsigned long best)
0204 {
0205     return abs(rate - now) < abs(rate - best);
0206 }
0207 
0208 static int ep93xx_mux_determine_rate(struct clk_hw *hw,
0209                 struct clk_rate_request *req)
0210 {
0211     unsigned long rate = req->rate;
0212     struct clk *best_parent = NULL;
0213     unsigned long __parent_rate;
0214     unsigned long best_rate = 0, actual_rate, mclk_rate;
0215     unsigned long best_parent_rate;
0216     int __div = 0, __pdiv = 0;
0217     int i;
0218 
0219     /*
0220      * Try the two pll's and the external clock
0221      * Because the valid predividers are 2, 2.5 and 3, we multiply
0222      * all the clocks by 2 to avoid floating point math.
0223      *
0224      * This is based on the algorithm in the ep93xx raster guide:
0225      * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
0226      *
0227      */
0228     for (i = 0; i < ARRAY_SIZE(mux_parents); i++) {
0229         struct clk *parent = clk_get_sys(mux_parents[i], NULL);
0230 
0231         __parent_rate = clk_get_rate(parent);
0232         mclk_rate = __parent_rate * 2;
0233 
0234         /* Try each predivider value */
0235         for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
0236             __div = mclk_rate / (rate * __pdiv);
0237             if (__div < 2 || __div > 127)
0238                 continue;
0239 
0240             actual_rate = mclk_rate / (__pdiv * __div);
0241             if (is_best(rate, actual_rate, best_rate)) {
0242                 best_rate = actual_rate;
0243                 best_parent_rate = __parent_rate;
0244                 best_parent = parent;
0245             }
0246         }
0247     }
0248 
0249     if (!best_parent)
0250         return -EINVAL;
0251 
0252     req->best_parent_rate = best_parent_rate;
0253     req->best_parent_hw = __clk_get_hw(best_parent);
0254     req->rate = best_rate;
0255 
0256     return 0;
0257 }
0258 
0259 static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw,
0260                         unsigned long parent_rate)
0261 {
0262     struct clk_psc *psc = to_clk_psc(hw);
0263     unsigned long rate = 0;
0264     u32 val = __raw_readl(psc->reg);
0265     int __pdiv = ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03);
0266     int __div = val & 0x7f;
0267 
0268     if (__div > 0)
0269         rate = (parent_rate * 2) / ((__pdiv + 3) * __div);
0270 
0271     return rate;
0272 }
0273 
0274 static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
0275                 unsigned long parent_rate)
0276 {
0277     struct clk_psc *psc = to_clk_psc(hw);
0278     int pdiv = 0, div = 0;
0279     unsigned long best_rate = 0, actual_rate, mclk_rate;
0280     int __div = 0, __pdiv = 0;
0281     u32 val;
0282 
0283     mclk_rate = parent_rate * 2;
0284 
0285     for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
0286         __div = mclk_rate / (rate * __pdiv);
0287         if (__div < 2 || __div > 127)
0288             continue;
0289 
0290         actual_rate = mclk_rate / (__pdiv * __div);
0291         if (is_best(rate, actual_rate, best_rate)) {
0292             pdiv = __pdiv - 3;
0293             div = __div;
0294             best_rate = actual_rate;
0295         }
0296     }
0297 
0298     if (!best_rate)
0299         return -EINVAL;
0300 
0301     val = __raw_readl(psc->reg);
0302 
0303     /* Clear old dividers */
0304     val &= ~0x37f;
0305 
0306     /* Set the new pdiv and div bits for the new clock rate */
0307     val |= (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
0308     ep93xx_syscon_swlocked_write(val, psc->reg);
0309 
0310     return 0;
0311 }
0312 
0313 static const struct clk_ops clk_ddiv_ops = {
0314     .enable = ep93xx_clk_enable,
0315     .disable = ep93xx_clk_disable,
0316     .is_enabled = ep93xx_clk_is_enabled,
0317     .get_parent = ep93xx_mux_get_parent,
0318     .set_parent = ep93xx_mux_set_parent_lock,
0319     .determine_rate = ep93xx_mux_determine_rate,
0320     .recalc_rate = ep93xx_ddiv_recalc_rate,
0321     .set_rate = ep93xx_ddiv_set_rate,
0322 };
0323 
0324 static struct clk_hw *clk_hw_register_ddiv(const char *name,
0325                       void __iomem *reg,
0326                       u8 bit_idx)
0327 {
0328     struct clk_init_data init;
0329     struct clk_psc *psc;
0330     struct clk *clk;
0331 
0332     psc = kzalloc(sizeof(*psc), GFP_KERNEL);
0333     if (!psc)
0334         return ERR_PTR(-ENOMEM);
0335 
0336     init.name = name;
0337     init.ops = &clk_ddiv_ops;
0338     init.flags = 0;
0339     init.parent_names = mux_parents;
0340     init.num_parents = ARRAY_SIZE(mux_parents);
0341 
0342     psc->reg = reg;
0343     psc->bit_idx = bit_idx;
0344     psc->lock = &clk_lock;
0345     psc->hw.init = &init;
0346 
0347     clk = clk_register(NULL, &psc->hw);
0348     if (IS_ERR(clk)) {
0349         kfree(psc);
0350         return ERR_CAST(clk);
0351     }
0352     return &psc->hw;
0353 }
0354 
0355 static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw,
0356                         unsigned long parent_rate)
0357 {
0358     struct clk_psc *psc = to_clk_psc(hw);
0359     u32 val = __raw_readl(psc->reg);
0360     u8 index = (val & psc->mask) >> psc->shift;
0361 
0362     if (index > psc->num_div)
0363         return 0;
0364 
0365     return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]);
0366 }
0367 
0368 static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate,
0369                    unsigned long *parent_rate)
0370 {
0371     struct clk_psc *psc = to_clk_psc(hw);
0372     unsigned long best = 0, now, maxdiv;
0373     int i;
0374 
0375     maxdiv = psc->div[psc->num_div - 1];
0376 
0377     for (i = 0; i < psc->num_div; i++) {
0378         if ((rate * psc->div[i]) == *parent_rate)
0379             return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]);
0380 
0381         now = DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]);
0382 
0383         if (is_best(rate, now, best))
0384             best = now;
0385     }
0386 
0387     if (!best)
0388         best = DIV_ROUND_UP_ULL(*parent_rate, maxdiv);
0389 
0390     return best;
0391 }
0392 
0393 static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate,
0394                    unsigned long parent_rate)
0395 {
0396     struct clk_psc *psc = to_clk_psc(hw);
0397     u32 val = __raw_readl(psc->reg) & ~psc->mask;
0398     int i;
0399 
0400     for (i = 0; i < psc->num_div; i++)
0401         if (rate == parent_rate / psc->div[i]) {
0402             val |= i << psc->shift;
0403             break;
0404         }
0405 
0406     if (i == psc->num_div)
0407         return -EINVAL;
0408 
0409     ep93xx_syscon_swlocked_write(val, psc->reg);
0410 
0411     return 0;
0412 }
0413 
0414 static const struct clk_ops ep93xx_div_ops = {
0415     .enable = ep93xx_clk_enable,
0416     .disable = ep93xx_clk_disable,
0417     .is_enabled = ep93xx_clk_is_enabled,
0418     .recalc_rate = ep93xx_div_recalc_rate,
0419     .round_rate = ep93xx_div_round_rate,
0420     .set_rate = ep93xx_div_set_rate,
0421 };
0422 
0423 static struct clk_hw *clk_hw_register_div(const char *name,
0424                       const char *parent_name,
0425                       void __iomem *reg,
0426                       u8 enable_bit,
0427                       u8 shift,
0428                       u8 width,
0429                       char *clk_divisors,
0430                       u8 num_div)
0431 {
0432     struct clk_init_data init;
0433     struct clk_psc *psc;
0434     struct clk *clk;
0435 
0436     psc = kzalloc(sizeof(*psc), GFP_KERNEL);
0437     if (!psc)
0438         return ERR_PTR(-ENOMEM);
0439 
0440     init.name = name;
0441     init.ops = &ep93xx_div_ops;
0442     init.flags = 0;
0443     init.parent_names = (parent_name ? &parent_name : NULL);
0444     init.num_parents = 1;
0445 
0446     psc->reg = reg;
0447     psc->bit_idx = enable_bit;
0448     psc->mask = GENMASK(shift + width - 1, shift);
0449     psc->shift = shift;
0450     psc->div = clk_divisors;
0451     psc->num_div = num_div;
0452     psc->lock = &clk_lock;
0453     psc->hw.init = &init;
0454 
0455     clk = clk_register(NULL, &psc->hw);
0456     if (IS_ERR(clk)) {
0457         kfree(psc);
0458         return ERR_CAST(clk);
0459     }
0460     return &psc->hw;
0461 }
0462 
0463 struct ep93xx_gate {
0464     unsigned int bit;
0465     const char *dev_id;
0466     const char *con_id;
0467 };
0468 
0469 static struct ep93xx_gate ep93xx_uarts[] = {
0470     {EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL},
0471     {EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL},
0472     {EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL},
0473 };
0474 
0475 static void __init ep93xx_uart_clock_init(void)
0476 {
0477     unsigned int i;
0478     struct clk_hw *hw;
0479     u32 value;
0480     unsigned int clk_uart_div;
0481 
0482     value = __raw_readl(EP93XX_SYSCON_PWRCNT);
0483     if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
0484         clk_uart_div = 1;
0485     else
0486         clk_uart_div = 2;
0487 
0488     hw = clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart_div);
0489 
0490     /* parenting uart gate clocks to uart clock */
0491     for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) {
0492         hw = ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id,
0493                     "uart",
0494                     EP93XX_SYSCON_DEVCFG,
0495                     ep93xx_uarts[i].bit);
0496 
0497         clk_hw_register_clkdev(hw, NULL, ep93xx_uarts[i].dev_id);
0498     }
0499 }
0500 
0501 static struct ep93xx_gate ep93xx_dmas[] = {
0502     {EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"},
0503     {EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"},
0504     {EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"},
0505     {EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"},
0506     {EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"},
0507     {EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"},
0508     {EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"},
0509     {EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"},
0510     {EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"},
0511     {EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"},
0512     {EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"},
0513     {EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"},
0514 };
0515 
0516 static void __init ep93xx_dma_clock_init(void)
0517 {
0518     unsigned int i;
0519     struct clk_hw *hw;
0520     int ret;
0521 
0522     for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) {
0523         hw = clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id,
0524                     "hclk", 0,
0525                     EP93XX_SYSCON_PWRCNT,
0526                     ep93xx_dmas[i].bit,
0527                     0,
0528                     &clk_lock);
0529 
0530         ret = clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL);
0531         if (ret)
0532             pr_err("%s: failed to register lookup %s\n",
0533                    __func__, ep93xx_dmas[i].con_id);
0534     }
0535 }
0536 
0537 static int __init ep93xx_clock_init(void)
0538 {
0539     u32 value;
0540     struct clk_hw *hw;
0541     unsigned long clk_pll1_rate;
0542     unsigned long clk_f_rate;
0543     unsigned long clk_h_rate;
0544     unsigned long clk_p_rate;
0545     unsigned long clk_pll2_rate;
0546     unsigned int clk_f_div;
0547     unsigned int clk_h_div;
0548     unsigned int clk_p_div;
0549     unsigned int clk_usb_div;
0550     unsigned long clk_spi_div;
0551 
0552     hw = clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_RATE);
0553     clk_hw_register_clkdev(hw, NULL, "xtali");
0554 
0555     /* Determine the bootloader configured pll1 rate */
0556     value = __raw_readl(EP93XX_SYSCON_CLKSET1);
0557     if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
0558         clk_pll1_rate = EP93XX_EXT_CLK_RATE;
0559     else
0560         clk_pll1_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
0561 
0562     hw = clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate);
0563     clk_hw_register_clkdev(hw, NULL, "pll1");
0564 
0565     /* Initialize the pll1 derived clocks */
0566     clk_f_div = fclk_divisors[(value >> 25) & 0x7];
0567     clk_h_div = hclk_divisors[(value >> 20) & 0x7];
0568     clk_p_div = pclk_divisors[(value >> 18) & 0x3];
0569 
0570     hw = clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div);
0571     clk_f_rate = clk_get_rate(hw->clk);
0572     hw = clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div);
0573     clk_h_rate = clk_get_rate(hw->clk);
0574     hw = clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div);
0575     clk_p_rate = clk_get_rate(hw->clk);
0576 
0577     clk_hw_register_clkdev(hw, "apb_pclk", NULL);
0578 
0579     ep93xx_dma_clock_init();
0580 
0581     /* Determine the bootloader configured pll2 rate */
0582     value = __raw_readl(EP93XX_SYSCON_CLKSET2);
0583     if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
0584         clk_pll2_rate = EP93XX_EXT_CLK_RATE;
0585     else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
0586         clk_pll2_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
0587     else
0588         clk_pll2_rate = 0;
0589 
0590     hw = clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate);
0591     clk_hw_register_clkdev(hw, NULL, "pll2");
0592 
0593     /* Initialize the pll2 derived clocks */
0594     /*
0595      * These four bits set the divide ratio between the PLL2
0596      * output and the USB clock.
0597      * 0000 - Divide by 1
0598      * 0001 - Divide by 2
0599      * 0010 - Divide by 3
0600      * 0011 - Divide by 4
0601      * 0100 - Divide by 5
0602      * 0101 - Divide by 6
0603      * 0110 - Divide by 7
0604      * 0111 - Divide by 8
0605      * 1000 - Divide by 9
0606      * 1001 - Divide by 10
0607      * 1010 - Divide by 11
0608      * 1011 - Divide by 12
0609      * 1100 - Divide by 13
0610      * 1101 - Divide by 14
0611      * 1110 - Divide by 15
0612      * 1111 - Divide by 1
0613      * On power-on-reset these bits are reset to 0000b.
0614      */
0615     clk_usb_div = (((value >> 28) & 0xf) + 1);
0616     hw = clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_usb_div);
0617     hw = clk_hw_register_gate(NULL, "ohci-platform",
0618                 "usb_clk", 0,
0619                 EP93XX_SYSCON_PWRCNT,
0620                 EP93XX_SYSCON_PWRCNT_USH_EN,
0621                 0,
0622                 &clk_lock);
0623     clk_hw_register_clkdev(hw, NULL, "ohci-platform");
0624 
0625     /*
0626      * EP93xx SSP clock rate was doubled in version E2. For more information
0627      * see:
0628      *     http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
0629      */
0630     clk_spi_div = 1;
0631     if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
0632         clk_spi_div = 2;
0633     hw = clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, clk_spi_div);
0634     clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0");
0635 
0636     /* pwm clock */
0637     hw = clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1);
0638     clk_hw_register_clkdev(hw, "pwm_clk", NULL);
0639 
0640     pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
0641         clk_pll1_rate / 1000000, clk_pll2_rate / 1000000);
0642     pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
0643         clk_f_rate / 1000000, clk_h_rate / 1000000,
0644         clk_p_rate / 1000000);
0645 
0646     ep93xx_uart_clock_init();
0647 
0648     /* touchscreen/adc clock */
0649     hw = clk_hw_register_div("ep93xx-adc",
0650                 "xtali",
0651                 EP93XX_SYSCON_KEYTCHCLKDIV,
0652                 EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
0653                 EP93XX_SYSCON_KEYTCHCLKDIV_ADIV,
0654                 1,
0655                 adc_divisors,
0656                 ARRAY_SIZE(adc_divisors));
0657 
0658     clk_hw_register_clkdev(hw, NULL, "ep93xx-adc");
0659 
0660     /* keypad clock */
0661     hw = clk_hw_register_div("ep93xx-keypad",
0662                 "xtali",
0663                 EP93XX_SYSCON_KEYTCHCLKDIV,
0664                 EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
0665                 EP93XX_SYSCON_KEYTCHCLKDIV_KDIV,
0666                 1,
0667                 adc_divisors,
0668                 ARRAY_SIZE(adc_divisors));
0669 
0670     clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad");
0671 
0672     /* On reset PDIV and VDIV is set to zero, while PDIV zero
0673      * means clock disable, VDIV shouldn't be zero.
0674      * So i set both dividers to minimum.
0675      */
0676     /* ENA - Enable CLK divider. */
0677     /* PDIV - 00 - Disable clock */
0678     /* VDIV - at least 2 */
0679     /* Check and enable video clk registers */
0680     value = __raw_readl(EP93XX_SYSCON_VIDCLKDIV);
0681     value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
0682     ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV);
0683 
0684     /* check and enable i2s clk registers */
0685     value = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
0686     value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
0687     ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV);
0688 
0689     /* video clk */
0690     hw = clk_hw_register_ddiv("ep93xx-fb",
0691                 EP93XX_SYSCON_VIDCLKDIV,
0692                 EP93XX_SYSCON_CLKDIV_ENABLE);
0693 
0694     clk_hw_register_clkdev(hw, NULL, "ep93xx-fb");
0695 
0696     /* i2s clk */
0697     hw = clk_hw_register_ddiv("mclk",
0698                 EP93XX_SYSCON_I2SCLKDIV,
0699                 EP93XX_SYSCON_CLKDIV_ENABLE);
0700 
0701     clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s");
0702 
0703     /* i2s sclk */
0704 #define EP93XX_I2SCLKDIV_SDIV_SHIFT 16
0705 #define EP93XX_I2SCLKDIV_SDIV_WIDTH 1
0706     hw = clk_hw_register_div("sclk",
0707                 "mclk",
0708                 EP93XX_SYSCON_I2SCLKDIV,
0709                 EP93XX_SYSCON_I2SCLKDIV_SENA,
0710                 EP93XX_I2SCLKDIV_SDIV_SHIFT,
0711                 EP93XX_I2SCLKDIV_SDIV_WIDTH,
0712                 sclk_divisors,
0713                 ARRAY_SIZE(sclk_divisors));
0714 
0715     clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s");
0716 
0717     /* i2s lrclk */
0718 #define EP93XX_I2SCLKDIV_LRDIV32_SHIFT  17
0719 #define EP93XX_I2SCLKDIV_LRDIV32_WIDTH  3
0720     hw = clk_hw_register_div("lrclk",
0721                 "sclk",
0722                 EP93XX_SYSCON_I2SCLKDIV,
0723                 EP93XX_SYSCON_I2SCLKDIV_SENA,
0724                 EP93XX_I2SCLKDIV_LRDIV32_SHIFT,
0725                 EP93XX_I2SCLKDIV_LRDIV32_WIDTH,
0726                 lrclk_divisors,
0727                 ARRAY_SIZE(lrclk_divisors));
0728 
0729     clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s");
0730 
0731     return 0;
0732 }
0733 postcore_initcall(ep93xx_clock_init);
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