0001
0002
0003 #ifndef __ASM_ARCH_PM_H
0004 #define __ASM_ARCH_PM_H
0005
0006 #include <asm/errno.h>
0007 #include "irqs.h"
0008
0009 #define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
0010 #define CLOCK_GATING_BIT_USB0 0
0011 #define CLOCK_GATING_BIT_USB1 1
0012 #define CLOCK_GATING_BIT_GBE 2
0013 #define CLOCK_GATING_BIT_SATA 3
0014 #define CLOCK_GATING_BIT_PCIE0 4
0015 #define CLOCK_GATING_BIT_PCIE1 5
0016 #define CLOCK_GATING_BIT_SDIO0 8
0017 #define CLOCK_GATING_BIT_SDIO1 9
0018 #define CLOCK_GATING_BIT_NAND 10
0019 #define CLOCK_GATING_BIT_CAMERA 11
0020 #define CLOCK_GATING_BIT_I2S0 12
0021 #define CLOCK_GATING_BIT_I2S1 13
0022 #define CLOCK_GATING_BIT_CRYPTO 15
0023 #define CLOCK_GATING_BIT_AC97 21
0024 #define CLOCK_GATING_BIT_PDMA 22
0025 #define CLOCK_GATING_BIT_XOR0 23
0026 #define CLOCK_GATING_BIT_XOR1 24
0027 #define CLOCK_GATING_BIT_GIGA_PHY 30
0028 #define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
0029 #define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
0030 #define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
0031 #define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
0032 #define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
0033 #define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
0034 #define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
0035 #define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
0036 #define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
0037 #define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
0038 #define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
0039 #define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
0040 #define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
0041 #define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
0042 #define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
0043 #define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
0044 #define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
0045 #define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
0046
0047 #define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
0048
0049 #define PMU_SW_RST_VIDEO_MASK BIT(16)
0050 #define PMU_SW_RST_GPU_MASK BIT(18)
0051
0052 #define PMU_PWR_GPU_PWR_DWN_MASK BIT(2)
0053 #define PMU_PWR_VPU_PWR_DWN_MASK BIT(3)
0054
0055 #define PMU_ISO_VIDEO_MASK BIT(0)
0056 #define PMU_ISO_GPU_MASK BIT(1)
0057
0058 #endif
