arm/mach-dove/pcie.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mach-dove/pcie.c
0004  *
0005  * PCIe functions for Marvell Dove 88AP510 SoC
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/pci.h>
0010 #include <linux/clk.h>
0011 #include <video/vga.h>
0012 #include <asm/mach/pci.h>
0013 #include <asm/mach/arch.h>
0014 #include <asm/setup.h>
0015 #include <asm/delay.h>
0016 #include <plat/pcie.h>
0017 #include <plat/addr-map.h>
0018 #include "irqs.h"
0019 #include "bridge-regs.h"
0020 #include "common.h"
0021
0022 struct pcie_port {
0023     u8          index;
0024     u8          root_bus_nr;
0025     void __iomem        *base;
0026     spinlock_t      conf_lock;
0027     char            mem_space_name[16];
0028     struct resource     res;
0029 };
0030
0031 static struct pcie_port pcie_port[2];
0032 static int num_pcie_ports;
0033
0034
0035 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
0036 {
0037     struct pcie_port *pp;
0038     struct resource realio;
0039
0040     if (nr >= num_pcie_ports)
0041         return 0;
0042
0043     pp = &pcie_port[nr];
0044     sys->private_data = pp;
0045     pp->root_bus_nr = sys->busnr;
0046
0047     /*
0048      * Generic PCIe unit setup.
0049      */
0050     orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
0051
0052     orion_pcie_setup(pp->base);
0053
0054     realio.start = sys->busnr * SZ_64K;
0055     realio.end = realio.start + SZ_64K - 1;
0056     pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
0057                             DOVE_PCIE1_IO_PHYS_BASE);
0058
0059     /*
0060      * IORESOURCE_MEM
0061      */
0062     snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
0063          "PCIe %d MEM", pp->index);
0064     pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
0065     pp->res.name = pp->mem_space_name;
0066     if (pp->index == 0) {
0067         pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
0068         pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
0069     } else {
0070         pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
0071         pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
0072     }
0073     pp->res.flags = IORESOURCE_MEM;
0074     if (request_resource(&iomem_resource, &pp->res))
0075         panic("Request PCIe Memory resource failed\n");
0076     pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
0077
0078     return 1;
0079 }
0080
0081 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
0082 {
0083     /*
0084      * Don't go out when trying to access nonexisting devices
0085      * on the local bus.
0086      */
0087     if (bus == pp->root_bus_nr && dev > 1)
0088         return 0;
0089
0090     return 1;
0091 }
0092
0093 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
0094             int size, u32 *val)
0095 {
0096     struct pci_sys_data *sys = bus->sysdata;
0097     struct pcie_port *pp = sys->private_data;
0098     unsigned long flags;
0099     int ret;
0100
0101     if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
0102         *val = 0xffffffff;
0103         return PCIBIOS_DEVICE_NOT_FOUND;
0104     }
0105
0106     spin_lock_irqsave(&pp->conf_lock, flags);
0107     ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
0108     spin_unlock_irqrestore(&pp->conf_lock, flags);
0109
0110     return ret;
0111 }
0112
0113 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
0114             int where, int size, u32 val)
0115 {
0116     struct pci_sys_data *sys = bus->sysdata;
0117     struct pcie_port *pp = sys->private_data;
0118     unsigned long flags;
0119     int ret;
0120
0121     if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
0122         return PCIBIOS_DEVICE_NOT_FOUND;
0123
0124     spin_lock_irqsave(&pp->conf_lock, flags);
0125     ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
0126     spin_unlock_irqrestore(&pp->conf_lock, flags);
0127
0128     return ret;
0129 }
0130
0131 static struct pci_ops pcie_ops = {
0132     .read = pcie_rd_conf,
0133     .write = pcie_wr_conf,
0134 };
0135
0136 /*
0137  * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
0138  * is operating as a root complex this needs to be switched to
0139  * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
0140  * the device. Decoding setup is handled by the orion code.
0141  */
0142 static void rc_pci_fixup(struct pci_dev *dev)
0143 {
0144     if (dev->bus->parent == NULL && dev->devfn == 0) {
0145         int i;
0146
0147         dev->class &= 0xff;
0148         dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
0149         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
0150             dev->resource[i].start = 0;
0151             dev->resource[i].end   = 0;
0152             dev->resource[i].flags = 0;
0153         }
0154     }
0155 }
0156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
0157
0158 static int __init
0159 dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
0160 {
0161     struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
0162
0163     if (nr >= num_pcie_ports) {
0164         BUG();
0165         return -EINVAL;
0166     }
0167
0168     list_splice_init(&sys->resources, &bridge->windows);
0169     bridge->dev.parent = NULL;
0170     bridge->sysdata = sys;
0171     bridge->busnr = sys->busnr;
0172     bridge->ops = &pcie_ops;
0173
0174     return pci_scan_root_bus_bridge(bridge);
0175 }
0176
0177 static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0178 {
0179     struct pci_sys_data *sys = dev->sysdata;
0180     struct pcie_port *pp = sys->private_data;
0181
0182     return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
0183 }
0184
0185 static struct hw_pci dove_pci __initdata = {
0186     .nr_controllers = 2,
0187     .setup      = dove_pcie_setup,
0188     .scan       = dove_pcie_scan_bus,
0189     .map_irq    = dove_pcie_map_irq,
0190 };
0191
0192 static void __init add_pcie_port(int index, void __iomem *base)
0193 {
0194     printk(KERN_INFO "Dove PCIe port %d: ", index);
0195
0196     if (orion_pcie_link_up(base)) {
0197         struct pcie_port *pp = &pcie_port[num_pcie_ports++];
0198         struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
0199
0200         if (!IS_ERR(clk))
0201             clk_prepare_enable(clk);
0202
0203         printk(KERN_INFO "link up\n");
0204
0205         pp->index = index;
0206         pp->root_bus_nr = -1;
0207         pp->base = base;
0208         spin_lock_init(&pp->conf_lock);
0209         memset(&pp->res, 0, sizeof(pp->res));
0210     } else {
0211         printk(KERN_INFO "link down, ignoring\n");
0212     }
0213 }
0214
0215 void __init dove_pcie_init(int init_port0, int init_port1)
0216 {
0217     vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
0218
0219     if (init_port0)
0220         add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
0221
0222     if (init_port1)
0223         add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
0224
0225     pci_common_init(&dove_pci);
0226 }