arm/mach-dove/dove.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Generic definitions for Marvell Dove 88AP510 SoC */
0003
0004 #ifndef __ASM_ARCH_DOVE_H
0005 #define __ASM_ARCH_DOVE_H
0006
0007 #include "irqs.h"
0008
0009 /*
0010  * Marvell Dove address maps.
0011  *
0012  * phys     virt        size
0013  * c8000000 fdb00000    1M  Cryptographic SRAM
0014  * e0000000 @runtime    128M    PCIe-0 Memory space
0015  * e8000000 @runtime    128M    PCIe-1 Memory space
0016  * f1000000 fec00000    1M  on-chip south-bridge registers
0017  * f1800000 fe400000    8M  on-chip north-bridge registers
0018  * f2000000 fee00000    1M  PCIe-0 I/O space
0019  * f2100000 fef00000    1M  PCIe-1 I/O space
0020  */
0021
0022 #define DOVE_CESA_PHYS_BASE     0xc8000000
0023 #define DOVE_CESA_VIRT_BASE     IOMEM(0xfdb00000)
0024 #define DOVE_CESA_SIZE          SZ_1M
0025
0026 #define DOVE_PCIE0_MEM_PHYS_BASE    0xe0000000
0027 #define DOVE_PCIE0_MEM_SIZE     SZ_128M
0028
0029 #define DOVE_PCIE1_MEM_PHYS_BASE    0xe8000000
0030 #define DOVE_PCIE1_MEM_SIZE     SZ_128M
0031
0032 #define DOVE_BOOTROM_PHYS_BASE      0xf8000000
0033 #define DOVE_BOOTROM_SIZE       SZ_128M
0034
0035 #define DOVE_SCRATCHPAD_PHYS_BASE   0xf0000000
0036 #define DOVE_SCRATCHPAD_VIRT_BASE   IOMEM(0xfdd00000)
0037 #define DOVE_SCRATCHPAD_SIZE        SZ_1M
0038
0039 #define DOVE_SB_REGS_PHYS_BASE      0xf1000000
0040 #define DOVE_SB_REGS_VIRT_BASE      IOMEM(0xfec00000)
0041 #define DOVE_SB_REGS_SIZE       SZ_1M
0042
0043 #define DOVE_NB_REGS_PHYS_BASE      0xf1800000
0044 #define DOVE_NB_REGS_VIRT_BASE      IOMEM(0xfe400000)
0045 #define DOVE_NB_REGS_SIZE       SZ_8M
0046
0047 #define DOVE_PCIE0_IO_PHYS_BASE     0xf2000000
0048 #define DOVE_PCIE0_IO_BUS_BASE      0x00000000
0049 #define DOVE_PCIE0_IO_SIZE      SZ_64K
0050
0051 #define DOVE_PCIE1_IO_PHYS_BASE     0xf2100000
0052 #define DOVE_PCIE1_IO_BUS_BASE      0x00010000
0053 #define DOVE_PCIE1_IO_SIZE      SZ_64K
0054
0055 /*
0056  * Dove Core Registers Map
0057  */
0058
0059 /* SPI, I2C, UART */
0060 #define DOVE_I2C_PHYS_BASE  (DOVE_SB_REGS_PHYS_BASE + 0x11000)
0061 #define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12000)
0062 #define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12000)
0063 #define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12100)
0064 #define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12100)
0065 #define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12200)
0066 #define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12200)
0067 #define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12300)
0068 #define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12300)
0069 #define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
0070 #define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
0071
0072 /* North-South Bridge */
0073 #define BRIDGE_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x20000)
0074 #define BRIDGE_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x20000)
0075 #define  BRIDGE_WINS_BASE       (BRIDGE_PHYS_BASE)
0076 #define  BRIDGE_WINS_SZ         (0x80)
0077
0078 /* Cryptographic Engine */
0079 #define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x30000)
0080
0081 /* PCIe 0 */
0082 #define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x40000)
0083
0084 /* USB */
0085 #define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
0086 #define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
0087
0088 /* XOR 0 Engine */
0089 #define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
0090 #define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
0091 #define DOVE_XOR0_HIGH_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
0092 #define DOVE_XOR0_HIGH_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
0093
0094 /* XOR 1 Engine */
0095 #define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
0096 #define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
0097 #define DOVE_XOR1_HIGH_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
0098 #define DOVE_XOR1_HIGH_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
0099
0100 /* Gigabit Ethernet */
0101 #define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
0102
0103 /* PCIe 1 */
0104 #define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x80000)
0105
0106 /* CAFE */
0107 #define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x92000)
0108 #define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x90000)
0109 #define DOVE_CAM_PHYS_BASE  (DOVE_SB_REGS_PHYS_BASE + 0x94000)
0110 #define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
0111
0112 /* SATA */
0113 #define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
0114
0115 /* I2S/SPDIF */
0116 #define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
0117 #define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
0118
0119 /* NAND Flash Controller */
0120 #define DOVE_NFC_PHYS_BASE  (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
0121
0122 /* MPP, GPIO, Reset Sampling */
0123 #define DOVE_MPP_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
0124 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
0125 #define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE + 0x014)
0126 #define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE + 0x018)
0127 #define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
0128 #define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
0129 #define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
0130 #define DOVE_MPP_GENERAL_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
0131 #define  DOVE_AU1_SPDIFO_GPIO_EN    (1 << 1)
0132 #define  DOVE_NAND_GPIO_EN      (1 << 0)
0133 #define DOVE_MPP_CTRL4_VIRT_BASE    (DOVE_GPIO_LO_VIRT_BASE + 0x40)
0134 #define  DOVE_SPI_GPIO_SEL      (1 << 5)
0135 #define  DOVE_UART1_GPIO_SEL        (1 << 4)
0136 #define  DOVE_AU1_GPIO_SEL      (1 << 3)
0137 #define  DOVE_CAM_GPIO_SEL      (1 << 2)
0138 #define  DOVE_SD1_GPIO_SEL      (1 << 1)
0139 #define  DOVE_SD0_GPIO_SEL      (1 << 0)
0140
0141 /* Power Management */
0142 #define DOVE_PMU_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
0143 #define DOVE_PMU_SIG_CTRL   (DOVE_PMU_VIRT_BASE + 0x802c)
0144
0145 /* Real Time Clock */
0146 #define DOVE_RTC_PHYS_BASE  (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
0147
0148 /* AC97 */
0149 #define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
0150 #define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
0151
0152 /* Peripheral DMA */
0153 #define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
0154 #define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
0155
0156 #define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
0157 #define  DOVE_TWSI_ENABLE_OPTION1   (1 << 7)
0158 #define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
0159 #define  DOVE_TWSI_ENABLE_OPTION2   (1 << 20)
0160 #define  DOVE_TWSI_ENABLE_OPTION3   (1 << 21)
0161 #define  DOVE_TWSI_OPTION3_GPIO     (1 << 22)
0162 #define DOVE_SSP_PHYS_BASE  (DOVE_SB_REGS_PHYS_BASE + 0xec000)
0163 #define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
0164 #define  DOVE_SSP_ON_AU1        (1 << 0)
0165 #define  DOVE_SSP_CLOCK_ENABLE      (1 << 1)
0166 #define  DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
0167 /* Memory Controller */
0168 #define DOVE_MC_PHYS_BASE       (DOVE_NB_REGS_PHYS_BASE + 0x00000)
0169 #define  DOVE_MC_WINS_BASE      (DOVE_MC_PHYS_BASE + 0x100)
0170 #define  DOVE_MC_WINS_SZ        (0x8)
0171 #define DOVE_MC_VIRT_BASE   (DOVE_NB_REGS_VIRT_BASE + 0x00000)
0172
0173 /* LCD Controller */
0174 #define DOVE_LCD_PHYS_BASE  (DOVE_NB_REGS_PHYS_BASE + 0x10000)
0175 #define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
0176 #define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
0177 #define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
0178
0179 /* Graphic Engine */
0180 #define DOVE_GPU_PHYS_BASE  (DOVE_NB_REGS_PHYS_BASE + 0x40000)
0181
0182 /* Video Engine */
0183 #define DOVE_VPU_PHYS_BASE  (DOVE_NB_REGS_PHYS_BASE + 0x400000)
0184
0185 #endif