arm/mach-dove/common.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mach-dove/common.c
0004  *
0005  * Core functions for Marvell Dove 88AP510 System On Chip
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/platform_data/dma-mv_xor.h>
0015 #include <linux/platform_data/usb-ehci-orion.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/soc/dove/pmu.h>
0018 #include <asm/hardware/cache-tauros2.h>
0019 #include <asm/mach/arch.h>
0020 #include <asm/mach/map.h>
0021 #include <asm/mach/time.h>
0022 #include <plat/common.h>
0023 #include <plat/irq.h>
0024 #include <plat/time.h>
0025 #include "bridge-regs.h"
0026 #include "pm.h"
0027 #include "common.h"
0028
0029 /* These can go away once Dove uses the mvebu-mbus DT binding */
0030 #define DOVE_MBUS_PCIE0_MEM_TARGET    0x4
0031 #define DOVE_MBUS_PCIE0_MEM_ATTR      0xe8
0032 #define DOVE_MBUS_PCIE0_IO_TARGET     0x4
0033 #define DOVE_MBUS_PCIE0_IO_ATTR       0xe0
0034 #define DOVE_MBUS_PCIE1_MEM_TARGET    0x8
0035 #define DOVE_MBUS_PCIE1_MEM_ATTR      0xe8
0036 #define DOVE_MBUS_PCIE1_IO_TARGET     0x8
0037 #define DOVE_MBUS_PCIE1_IO_ATTR       0xe0
0038 #define DOVE_MBUS_CESA_TARGET         0x3
0039 #define DOVE_MBUS_CESA_ATTR           0x1
0040 #define DOVE_MBUS_BOOTROM_TARGET      0x1
0041 #define DOVE_MBUS_BOOTROM_ATTR        0xfd
0042 #define DOVE_MBUS_SCRATCHPAD_TARGET   0xd
0043 #define DOVE_MBUS_SCRATCHPAD_ATTR     0x0
0044
0045 /*****************************************************************************
0046  * I/O Address Mapping
0047  ****************************************************************************/
0048 static struct map_desc __maybe_unused dove_io_desc[] __initdata = {
0049     {
0050         .virtual    = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
0051         .pfn        = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
0052         .length     = DOVE_SB_REGS_SIZE,
0053         .type       = MT_DEVICE,
0054     }, {
0055         .virtual    = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
0056         .pfn        = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
0057         .length     = DOVE_NB_REGS_SIZE,
0058         .type       = MT_DEVICE,
0059     },
0060 };
0061
0062 void __init dove_map_io(void)
0063 {
0064     iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
0065 }
0066
0067 /*****************************************************************************
0068  * CLK tree
0069  ****************************************************************************/
0070 static int dove_tclk;
0071
0072 static DEFINE_SPINLOCK(gating_lock);
0073 static struct clk *tclk;
0074
0075 static struct clk __init *dove_register_gate(const char *name,
0076                          const char *parent, u8 bit_idx)
0077 {
0078     return clk_register_gate(NULL, name, parent, 0,
0079                  (void __iomem *)CLOCK_GATING_CONTROL,
0080                  bit_idx, 0, &gating_lock);
0081 }
0082
0083 static void __init dove_clk_init(void)
0084 {
0085     struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
0086     struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
0087     struct clk *xor0, *xor1, *ge, *gephy;
0088
0089     tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk);
0090
0091     usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
0092     usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
0093     sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
0094     pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
0095     pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
0096     sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
0097     sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
0098     nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
0099     camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
0100     i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
0101     i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
0102     crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
0103     ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
0104     pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
0105     xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
0106     xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
0107     gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
0108     ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
0109
0110     orion_clkdev_add(NULL, "orion_spi.0", tclk);
0111     orion_clkdev_add(NULL, "orion_spi.1", tclk);
0112     orion_clkdev_add(NULL, "orion_wdt", tclk);
0113     orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
0114
0115     orion_clkdev_add(NULL, "orion-ehci.0", usb0);
0116     orion_clkdev_add(NULL, "orion-ehci.1", usb1);
0117     orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
0118     orion_clkdev_add(NULL, "sata_mv.0", sata);
0119     orion_clkdev_add("0", "pcie", pex0);
0120     orion_clkdev_add("1", "pcie", pex1);
0121     orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
0122     orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
0123     orion_clkdev_add(NULL, "orion_nand", nand);
0124     orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
0125     orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
0126     orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
0127     orion_clkdev_add(NULL, "mv_crypto", crypto);
0128     orion_clkdev_add(NULL, "dove-ac97", ac97);
0129     orion_clkdev_add(NULL, "dove-pdma", pdma);
0130     orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
0131     orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
0132 }
0133
0134 /*****************************************************************************
0135  * EHCI0
0136  ****************************************************************************/
0137 void __init dove_ehci0_init(void)
0138 {
0139     orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
0140 }
0141
0142 /*****************************************************************************
0143  * EHCI1
0144  ****************************************************************************/
0145 void __init dove_ehci1_init(void)
0146 {
0147     orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
0148 }
0149
0150 /*****************************************************************************
0151  * GE00
0152  ****************************************************************************/
0153 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
0154 {
0155     orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
0156             IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
0157             1600);
0158 }
0159
0160 /*****************************************************************************
0161  * SoC RTC
0162  ****************************************************************************/
0163 static void __init dove_rtc_init(void)
0164 {
0165     orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
0166 }
0167
0168 /*****************************************************************************
0169  * SATA
0170  ****************************************************************************/
0171 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
0172 {
0173     orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
0174
0175 }
0176
0177 /*****************************************************************************
0178  * UART0
0179  ****************************************************************************/
0180 void __init dove_uart0_init(void)
0181 {
0182     orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
0183              IRQ_DOVE_UART_0, tclk);
0184 }
0185
0186 /*****************************************************************************
0187  * UART1
0188  ****************************************************************************/
0189 void __init dove_uart1_init(void)
0190 {
0191     orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
0192              IRQ_DOVE_UART_1, tclk);
0193 }
0194
0195 /*****************************************************************************
0196  * UART2
0197  ****************************************************************************/
0198 void __init dove_uart2_init(void)
0199 {
0200     orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
0201              IRQ_DOVE_UART_2, tclk);
0202 }
0203
0204 /*****************************************************************************
0205  * UART3
0206  ****************************************************************************/
0207 void __init dove_uart3_init(void)
0208 {
0209     orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
0210              IRQ_DOVE_UART_3, tclk);
0211 }
0212
0213 /*****************************************************************************
0214  * SPI
0215  ****************************************************************************/
0216 void __init dove_spi0_init(void)
0217 {
0218     orion_spi_init(DOVE_SPI0_PHYS_BASE);
0219 }
0220
0221 void __init dove_spi1_init(void)
0222 {
0223     orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
0224 }
0225
0226 /*****************************************************************************
0227  * I2C
0228  ****************************************************************************/
0229 void __init dove_i2c_init(void)
0230 {
0231     orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
0232 }
0233
0234 /*****************************************************************************
0235  * Time handling
0236  ****************************************************************************/
0237 void __init dove_init_early(void)
0238 {
0239     orion_time_set_base(TIMER_VIRT_BASE);
0240     mvebu_mbus_init("marvell,dove-mbus",
0241             BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
0242             DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
0243 }
0244
0245 static int __init dove_find_tclk(void)
0246 {
0247     return 166666667;
0248 }
0249
0250 void __init dove_timer_init(void)
0251 {
0252     dove_tclk = dove_find_tclk();
0253     orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
0254             IRQ_DOVE_BRIDGE, dove_tclk);
0255 }
0256
0257 /*****************************************************************************
0258  * XOR 0
0259  ****************************************************************************/
0260 static void __init dove_xor0_init(void)
0261 {
0262     orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
0263             IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
0264 }
0265
0266 /*****************************************************************************
0267  * XOR 1
0268  ****************************************************************************/
0269 static void __init dove_xor1_init(void)
0270 {
0271     orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
0272             IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
0273 }
0274
0275 /*****************************************************************************
0276  * SDIO
0277  ****************************************************************************/
0278 static u64 sdio_dmamask = DMA_BIT_MASK(32);
0279
0280 static struct resource dove_sdio0_resources[] = {
0281     {
0282         .start  = DOVE_SDIO0_PHYS_BASE,
0283         .end    = DOVE_SDIO0_PHYS_BASE + 0xff,
0284         .flags  = IORESOURCE_MEM,
0285     }, {
0286         .start  = IRQ_DOVE_SDIO0,
0287         .end    = IRQ_DOVE_SDIO0,
0288         .flags  = IORESOURCE_IRQ,
0289     },
0290 };
0291
0292 static struct platform_device dove_sdio0 = {
0293     .name       = "sdhci-dove",
0294     .id     = 0,
0295     .dev        = {
0296         .dma_mask       = &sdio_dmamask,
0297         .coherent_dma_mask  = DMA_BIT_MASK(32),
0298     },
0299     .resource   = dove_sdio0_resources,
0300     .num_resources  = ARRAY_SIZE(dove_sdio0_resources),
0301 };
0302
0303 void __init dove_sdio0_init(void)
0304 {
0305     platform_device_register(&dove_sdio0);
0306 }
0307
0308 static struct resource dove_sdio1_resources[] = {
0309     {
0310         .start  = DOVE_SDIO1_PHYS_BASE,
0311         .end    = DOVE_SDIO1_PHYS_BASE + 0xff,
0312         .flags  = IORESOURCE_MEM,
0313     }, {
0314         .start  = IRQ_DOVE_SDIO1,
0315         .end    = IRQ_DOVE_SDIO1,
0316         .flags  = IORESOURCE_IRQ,
0317     },
0318 };
0319
0320 static struct platform_device dove_sdio1 = {
0321     .name       = "sdhci-dove",
0322     .id     = 1,
0323     .dev        = {
0324         .dma_mask       = &sdio_dmamask,
0325         .coherent_dma_mask  = DMA_BIT_MASK(32),
0326     },
0327     .resource   = dove_sdio1_resources,
0328     .num_resources  = ARRAY_SIZE(dove_sdio1_resources),
0329 };
0330
0331 void __init dove_sdio1_init(void)
0332 {
0333     platform_device_register(&dove_sdio1);
0334 }
0335
0336 void __init dove_setup_cpu_wins(void)
0337 {
0338     /*
0339      * The PCIe windows will no longer be statically allocated
0340      * here once Dove is migrated to the pci-mvebu driver. The
0341      * non-PCIe windows will no longer be created here once Dove
0342      * fully moves to DT.
0343      */
0344     mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
0345                       DOVE_MBUS_PCIE0_IO_ATTR,
0346                       DOVE_PCIE0_IO_PHYS_BASE,
0347                       DOVE_PCIE0_IO_SIZE,
0348                       DOVE_PCIE0_IO_BUS_BASE);
0349     mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
0350                       DOVE_MBUS_PCIE1_IO_ATTR,
0351                       DOVE_PCIE1_IO_PHYS_BASE,
0352                       DOVE_PCIE1_IO_SIZE,
0353                       DOVE_PCIE1_IO_BUS_BASE);
0354     mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
0355                     DOVE_MBUS_PCIE0_MEM_ATTR,
0356                     DOVE_PCIE0_MEM_PHYS_BASE,
0357                     DOVE_PCIE0_MEM_SIZE);
0358     mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
0359                     DOVE_MBUS_PCIE1_MEM_ATTR,
0360                     DOVE_PCIE1_MEM_PHYS_BASE,
0361                     DOVE_PCIE1_MEM_SIZE);
0362     mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
0363                     DOVE_MBUS_CESA_ATTR,
0364                     DOVE_CESA_PHYS_BASE,
0365                     DOVE_CESA_SIZE);
0366     mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
0367                     DOVE_MBUS_BOOTROM_ATTR,
0368                     DOVE_BOOTROM_PHYS_BASE,
0369                     DOVE_BOOTROM_SIZE);
0370     mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
0371                     DOVE_MBUS_SCRATCHPAD_ATTR,
0372                     DOVE_SCRATCHPAD_PHYS_BASE,
0373                     DOVE_SCRATCHPAD_SIZE);
0374 }
0375
0376 static struct resource orion_wdt_resource[] = {
0377         DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
0378         DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
0379 };
0380
0381 static struct platform_device orion_wdt_device = {
0382     .name       = "orion_wdt",
0383     .id     = -1,
0384     .num_resources  = ARRAY_SIZE(orion_wdt_resource),
0385     .resource   = orion_wdt_resource,
0386 };
0387
0388 static void __init __maybe_unused orion_wdt_init(void)
0389 {
0390     platform_device_register(&orion_wdt_device);
0391 }
0392
0393 static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
0394     {
0395         .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
0396         .rst_mask = PMU_SW_RST_VIDEO_MASK,
0397         .iso_mask = PMU_ISO_VIDEO_MASK,
0398         .name = "vpu-domain",
0399     }, {
0400         .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
0401         .rst_mask = PMU_SW_RST_GPU_MASK,
0402         .iso_mask = PMU_ISO_GPU_MASK,
0403         .name = "gpu-domain",
0404     }, {
0405         /* sentinel */
0406     },
0407 };
0408
0409 static const struct dove_pmu_initdata pmu_data __initconst = {
0410     .pmc_base = DOVE_PMU_VIRT_BASE,
0411     .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
0412     .irq = IRQ_DOVE_PMU,
0413     .irq_domain_start = IRQ_DOVE_PMU_START,
0414     .domains = pmu_domains,
0415 };
0416
0417 void __init dove_init(void)
0418 {
0419     pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
0420         (dove_tclk + 499999) / 1000000);
0421
0422 #ifdef CONFIG_CACHE_TAUROS2
0423     tauros2_init(0);
0424 #endif
0425     dove_setup_cpu_wins();
0426
0427     /* Setup root of clk tree */
0428     dove_clk_init();
0429
0430     /* internal devices that every board has */
0431     dove_init_pmu_legacy(&pmu_data);
0432     dove_rtc_init();
0433     dove_xor0_init();
0434     dove_xor1_init();
0435 }
0436
0437 void dove_restart(enum reboot_mode mode, const char *cmd)
0438 {
0439     /*
0440      * Enable soft reset to assert RSTOUTn.
0441      */
0442     writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
0443
0444     /*
0445      * Assert soft reset.
0446      */
0447     writel(SOFT_RESET, SYSTEM_SOFT_RESET);
0448
0449     while (1)
0450         ;
0451 }