arm/mach-dove/bridge-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Mbus-L to Mbus Bridge Registers */
0003
0004 #ifndef __ASM_ARCH_BRIDGE_REGS_H
0005 #define __ASM_ARCH_BRIDGE_REGS_H
0006
0007 #include "dove.h"
0008
0009 #define CPU_CONFIG      (BRIDGE_VIRT_BASE + 0x0000)
0010
0011 #define CPU_CONTROL     (BRIDGE_VIRT_BASE + 0x0104)
0012 #define  CPU_CTRL_PCIE0_LINK    0x00000001
0013 #define  CPU_RESET      0x00000002
0014 #define  CPU_CTRL_PCIE1_LINK    0x00000008
0015
0016 #define RSTOUTn_MASK        (BRIDGE_VIRT_BASE + 0x0108)
0017 #define RSTOUTn_MASK_PHYS   (BRIDGE_PHYS_BASE + 0x0108)
0018 #define  SOFT_RESET_OUT_EN  0x00000004
0019
0020 #define SYSTEM_SOFT_RESET   (BRIDGE_VIRT_BASE + 0x010c)
0021 #define  SOFT_RESET     0x00000001
0022
0023 #define BRIDGE_CAUSE        (BRIDGE_VIRT_BASE + 0x0110)
0024 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
0025
0026 #define IRQ_VIRT_BASE       (BRIDGE_VIRT_BASE + 0x0200)
0027 #define IRQ_CAUSE_LOW_OFF   0x0000
0028 #define IRQ_MASK_LOW_OFF    0x0004
0029 #define FIQ_MASK_LOW_OFF    0x0008
0030 #define ENDPOINT_MASK_LOW_OFF   0x000c
0031 #define IRQ_CAUSE_HIGH_OFF  0x0010
0032 #define IRQ_MASK_HIGH_OFF   0x0014
0033 #define FIQ_MASK_HIGH_OFF   0x0018
0034 #define ENDPOINT_MASK_HIGH_OFF  0x001c
0035 #define PCIE_INTERRUPT_MASK_OFF 0x0020
0036
0037 #define IRQ_MASK_LOW        (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
0038 #define FIQ_MASK_LOW        (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
0039 #define ENDPOINT_MASK_LOW   (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
0040 #define IRQ_MASK_HIGH       (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
0041 #define FIQ_MASK_HIGH       (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
0042 #define ENDPOINT_MASK_HIGH  (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
0043 #define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
0044
0045 #define POWER_MANAGEMENT    (BRIDGE_VIRT_BASE + 0x011c)
0046
0047 #define TIMER_VIRT_BASE     (BRIDGE_VIRT_BASE + 0x0300)
0048 #define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
0049
0050 #endif