arm/mach-davinci/pm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * DaVinci Power Management Routines
0004  *
0005  * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/
0006  */
0007
0008 #include <linux/pm.h>
0009 #include <linux/suspend.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/clk.h>
0013 #include <linux/spinlock.h>
0014
0015 #include <asm/cacheflush.h>
0016 #include <asm/delay.h>
0017 #include <asm/io.h>
0018
0019 #include "common.h"
0020 #include "da8xx.h"
0021 #include "mux.h"
0022 #include "pm.h"
0023 #include "clock.h"
0024 #include "psc.h"
0025 #include "sram.h"
0026
0027 #define DA850_PLL1_BASE     0x01e1a000
0028 #define DEEPSLEEP_SLEEPCOUNT_MASK   0xFFFF
0029 #define DEEPSLEEP_SLEEPCOUNT        128
0030
0031 static void (*davinci_sram_suspend) (struct davinci_pm_config *);
0032 static struct davinci_pm_config pm_config = {
0033     .sleepcount = DEEPSLEEP_SLEEPCOUNT,
0034     .ddrpsc_num = DA8XX_LPSC1_EMIF3C,
0035 };
0036
0037 static void davinci_sram_push(void *dest, void *src, unsigned int size)
0038 {
0039     memcpy(dest, src, size);
0040     flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
0041 }
0042
0043 static void davinci_pm_suspend(void)
0044 {
0045     unsigned val;
0046
0047     if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
0048
0049         /* Switch CPU PLL to bypass mode */
0050         val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
0051         val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
0052         __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
0053
0054         udelay(PLL_BYPASS_TIME);
0055
0056         /* Powerdown CPU PLL */
0057         val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
0058         val |= PLLCTL_PLLPWRDN;
0059         __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
0060     }
0061
0062     /* Configure sleep count in deep sleep register */
0063     val = __raw_readl(pm_config.deepsleep_reg);
0064     val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
0065     val |= pm_config.sleepcount;
0066     __raw_writel(val, pm_config.deepsleep_reg);
0067
0068     /* System goes to sleep in this call */
0069     davinci_sram_suspend(&pm_config);
0070
0071     if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
0072
0073         /* put CPU PLL in reset */
0074         val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
0075         val &= ~PLLCTL_PLLRST;
0076         __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
0077
0078         /* put CPU PLL in power down */
0079         val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
0080         val &= ~PLLCTL_PLLPWRDN;
0081         __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
0082
0083         /* wait for CPU PLL reset */
0084         udelay(PLL_RESET_TIME);
0085
0086         /* bring CPU PLL out of reset */
0087         val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
0088         val |= PLLCTL_PLLRST;
0089         __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
0090
0091         /* Wait for CPU PLL to lock */
0092         udelay(PLL_LOCK_TIME);
0093
0094         /* Remove CPU PLL from bypass mode */
0095         val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
0096         val &= ~PLLCTL_PLLENSRC;
0097         val |= PLLCTL_PLLEN;
0098         __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
0099     }
0100 }
0101
0102 static int davinci_pm_enter(suspend_state_t state)
0103 {
0104     int ret = 0;
0105
0106     switch (state) {
0107     case PM_SUSPEND_MEM:
0108         davinci_pm_suspend();
0109         break;
0110     default:
0111         ret = -EINVAL;
0112     }
0113
0114     return ret;
0115 }
0116
0117 static const struct platform_suspend_ops davinci_pm_ops = {
0118     .enter      = davinci_pm_enter,
0119     .valid      = suspend_valid_only_mem,
0120 };
0121
0122 int __init davinci_pm_init(void)
0123 {
0124     int ret;
0125
0126     ret = davinci_cfg_reg(DA850_RTC_ALARM);
0127     if (ret)
0128         return ret;
0129
0130     pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
0131     pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
0132
0133     pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
0134     if (!pm_config.cpupll_reg_base)
0135         return -ENOMEM;
0136
0137     pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
0138     if (!pm_config.ddrpll_reg_base) {
0139         ret = -ENOMEM;
0140         goto no_ddrpll_mem;
0141     }
0142
0143     pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
0144     if (!pm_config.ddrpsc_reg_base) {
0145         ret = -ENOMEM;
0146         goto no_ddrpsc_mem;
0147     }
0148
0149     davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
0150     if (!davinci_sram_suspend) {
0151         pr_err("PM: cannot allocate SRAM memory\n");
0152         ret = -ENOMEM;
0153         goto no_sram_mem;
0154     }
0155
0156     davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
0157                         davinci_cpu_suspend_sz);
0158
0159     suspend_set_ops(&davinci_pm_ops);
0160
0161     return 0;
0162
0163 no_sram_mem:
0164     iounmap(pm_config.ddrpsc_reg_base);
0165 no_ddrpsc_mem:
0166     iounmap(pm_config.ddrpll_reg_base);
0167 no_ddrpll_mem:
0168     iounmap(pm_config.cpupll_reg_base);
0169     return ret;
0170 }