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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * TI DaVinci DM365 chip specific setup
0004  *
0005  * Copyright (C) 2009 Texas Instruments
0006  */
0007 
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk/davinci.h>
0010 #include <linux/clkdev.h>
0011 #include <linux/dma-mapping.h>
0012 #include <linux/dmaengine.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/irqchip/irq-davinci-aintc.h>
0016 #include <linux/platform_data/edma.h>
0017 #include <linux/platform_data/gpio-davinci.h>
0018 #include <linux/platform_data/keyscan-davinci.h>
0019 #include <linux/platform_data/spi-davinci.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/serial_8250.h>
0022 #include <linux/spi/spi.h>
0023 
0024 #include <clocksource/timer-davinci.h>
0025 
0026 #include <asm/mach/map.h>
0027 
0028 #include "common.h"
0029 #include "cputype.h"
0030 #include "serial.h"
0031 #include "asp.h"
0032 #include "davinci.h"
0033 #include "irqs.h"
0034 #include "mux.h"
0035 
0036 #define DM365_REF_FREQ      24000000    /* 24 MHz on the DM365 EVM */
0037 #define DM365_RTC_BASE          0x01c69000
0038 #define DM365_KEYSCAN_BASE      0x01c69400
0039 #define DM365_OSD_BASE          0x01c71c00
0040 #define DM365_VENC_BASE         0x01c71e00
0041 #define DAVINCI_DM365_VC_BASE       0x01d0c000
0042 #define DAVINCI_DMA_VC_TX       2
0043 #define DAVINCI_DMA_VC_RX       3
0044 #define DM365_EMAC_BASE         0x01d07000
0045 #define DM365_EMAC_MDIO_BASE        (DM365_EMAC_BASE + 0x4000)
0046 #define DM365_EMAC_CNTRL_OFFSET     0x0000
0047 #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
0048 #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
0049 #define DM365_EMAC_CNTRL_RAM_SIZE   0x2000
0050 
0051 #define INTMUX      0x18
0052 #define EVTMUX      0x1c
0053 
0054 
0055 static const struct mux_config dm365_pins[] = {
0056 #ifdef CONFIG_DAVINCI_MUX
0057 MUX_CFG(DM365,  MMCSD0,     0,   24,     1,   0,     false)
0058 
0059 MUX_CFG(DM365,  SD1_CLK,    0,   16,    3,    1,     false)
0060 MUX_CFG(DM365,  SD1_CMD,    4,   30,    3,    1,     false)
0061 MUX_CFG(DM365,  SD1_DATA3,  4,   28,    3,    1,     false)
0062 MUX_CFG(DM365,  SD1_DATA2,  4,   26,    3,    1,     false)
0063 MUX_CFG(DM365,  SD1_DATA1,  4,   24,    3,    1,     false)
0064 MUX_CFG(DM365,  SD1_DATA0,  4,   22,    3,    1,     false)
0065 
0066 MUX_CFG(DM365,  I2C_SDA,    3,   23,    3,    2,     false)
0067 MUX_CFG(DM365,  I2C_SCL,    3,   21,    3,    2,     false)
0068 
0069 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
0070 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
0071 MUX_CFG(DM365,  AEMIF_A3,   2,   2,     3,    1,     false)
0072 MUX_CFG(DM365,  AEMIF_A7,   2,   4,     3,    1,     false)
0073 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
0074 MUX_CFG(DM365,  AEMIF_CE0,  2,   7,     1,    0,     false)
0075 MUX_CFG(DM365,  AEMIF_CE1,  2,   8,     1,    0,     false)
0076 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
0077 
0078 MUX_CFG(DM365,  MCBSP0_BDX, 0,   23,    1,    1,     false)
0079 MUX_CFG(DM365,  MCBSP0_X,   0,   22,    1,    1,     false)
0080 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
0081 MUX_CFG(DM365,  MCBSP0_BDR, 0,   20,    1,    1,     false)
0082 MUX_CFG(DM365,  MCBSP0_R,   0,   19,    1,    1,     false)
0083 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
0084 
0085 MUX_CFG(DM365,  SPI0_SCLK,  3,   28,    1,    1,     false)
0086 MUX_CFG(DM365,  SPI0_SDI,   3,   26,    3,    1,     false)
0087 MUX_CFG(DM365,  SPI0_SDO,   3,   25,    1,    1,     false)
0088 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
0089 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
0090 
0091 MUX_CFG(DM365,  UART0_RXD,  3,   20,    1,    1,     false)
0092 MUX_CFG(DM365,  UART0_TXD,  3,   19,    1,    1,     false)
0093 MUX_CFG(DM365,  UART1_RXD,  3,   17,    3,    2,     false)
0094 MUX_CFG(DM365,  UART1_TXD,  3,   15,    3,    2,     false)
0095 MUX_CFG(DM365,  UART1_RTS,  3,   23,    3,    1,     false)
0096 MUX_CFG(DM365,  UART1_CTS,  3,   21,    3,    1,     false)
0097 
0098 MUX_CFG(DM365,  EMAC_TX_EN, 3,   17,    3,    1,     false)
0099 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
0100 MUX_CFG(DM365,  EMAC_COL,   3,   14,    1,    1,     false)
0101 MUX_CFG(DM365,  EMAC_TXD3,  3,   13,    1,    1,     false)
0102 MUX_CFG(DM365,  EMAC_TXD2,  3,   12,    1,    1,     false)
0103 MUX_CFG(DM365,  EMAC_TXD1,  3,   11,    1,    1,     false)
0104 MUX_CFG(DM365,  EMAC_TXD0,  3,   10,    1,    1,     false)
0105 MUX_CFG(DM365,  EMAC_RXD3,  3,   9,     1,    1,     false)
0106 MUX_CFG(DM365,  EMAC_RXD2,  3,   8,     1,    1,     false)
0107 MUX_CFG(DM365,  EMAC_RXD1,  3,   7,     1,    1,     false)
0108 MUX_CFG(DM365,  EMAC_RXD0,  3,   6,     1,    1,     false)
0109 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
0110 MUX_CFG(DM365,  EMAC_RX_DV, 3,   4,     1,    1,     false)
0111 MUX_CFG(DM365,  EMAC_RX_ER, 3,   3,     1,    1,     false)
0112 MUX_CFG(DM365,  EMAC_CRS,   3,   2,     1,    1,     false)
0113 MUX_CFG(DM365,  EMAC_MDIO,  3,   1,     1,    1,     false)
0114 MUX_CFG(DM365,  EMAC_MDCLK, 3,   0,     1,    1,     false)
0115 
0116 MUX_CFG(DM365,  KEYSCAN,    2,   0,     0x3f, 0x3f,  false)
0117 
0118 MUX_CFG(DM365,  PWM0,       1,   0,     3,    2,     false)
0119 MUX_CFG(DM365,  PWM0_G23,   3,   26,    3,    3,     false)
0120 MUX_CFG(DM365,  PWM1,       1,   2,     3,    2,     false)
0121 MUX_CFG(DM365,  PWM1_G25,   3,   29,    3,    2,     false)
0122 MUX_CFG(DM365,  PWM2_G87,   1,   10,    3,    2,     false)
0123 MUX_CFG(DM365,  PWM2_G88,   1,   8,     3,    2,     false)
0124 MUX_CFG(DM365,  PWM2_G89,   1,   6,     3,    2,     false)
0125 MUX_CFG(DM365,  PWM2_G90,   1,   4,     3,    2,     false)
0126 MUX_CFG(DM365,  PWM3_G80,   1,   20,    3,    3,     false)
0127 MUX_CFG(DM365,  PWM3_G81,   1,   18,    3,    3,     false)
0128 MUX_CFG(DM365,  PWM3_G85,   1,   14,    3,    2,     false)
0129 MUX_CFG(DM365,  PWM3_G86,   1,   12,    3,    2,     false)
0130 
0131 MUX_CFG(DM365,  SPI1_SCLK,  4,   2,     3,    1,     false)
0132 MUX_CFG(DM365,  SPI1_SDI,   3,   31,    1,    1,     false)
0133 MUX_CFG(DM365,  SPI1_SDO,   4,   0,     3,    1,     false)
0134 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
0135 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
0136 
0137 MUX_CFG(DM365,  SPI2_SCLK,  4,   10,    3,    1,     false)
0138 MUX_CFG(DM365,  SPI2_SDI,   4,   6,     3,    1,     false)
0139 MUX_CFG(DM365,  SPI2_SDO,   4,   8,     3,    1,     false)
0140 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
0141 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
0142 
0143 MUX_CFG(DM365,  SPI3_SCLK,  0,   0,     3,    2,     false)
0144 MUX_CFG(DM365,  SPI3_SDI,   0,   2,     3,    2,     false)
0145 MUX_CFG(DM365,  SPI3_SDO,   0,   6,     3,    2,     false)
0146 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
0147 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
0148 
0149 MUX_CFG(DM365,  SPI4_SCLK,  4,   18,    3,    1,     false)
0150 MUX_CFG(DM365,  SPI4_SDI,   4,   14,    3,    1,     false)
0151 MUX_CFG(DM365,  SPI4_SDO,   4,   16,    3,    1,     false)
0152 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
0153 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
0154 
0155 MUX_CFG(DM365,  CLKOUT0,    4,   20,    3,    3,     false)
0156 MUX_CFG(DM365,  CLKOUT1,    4,   16,    3,    3,     false)
0157 MUX_CFG(DM365,  CLKOUT2,    4,   8,     3,    3,     false)
0158 
0159 MUX_CFG(DM365,  GPIO20,     3,   21,    3,    0,     false)
0160 MUX_CFG(DM365,  GPIO30,     4,   6,     3,    0,     false)
0161 MUX_CFG(DM365,  GPIO31,     4,   8,     3,    0,     false)
0162 MUX_CFG(DM365,  GPIO32,     4,   10,    3,    0,     false)
0163 MUX_CFG(DM365,  GPIO33,     4,   12,    3,    0,     false)
0164 MUX_CFG(DM365,  GPIO40,     4,   26,    3,    0,     false)
0165 MUX_CFG(DM365,  GPIO64_57,  2,   6,     1,    0,     false)
0166 
0167 MUX_CFG(DM365,  VOUT_FIELD, 1,   18,    3,    1,     false)
0168 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
0169 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
0170 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
0171 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
0172 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
0173 MUX_CFG(DM365,  VIN_CAM_VD, 0,   13,    1,    0,     false)
0174 MUX_CFG(DM365,  VIN_CAM_HD, 0,   12,    1,    0,     false)
0175 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
0176 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
0177 
0178 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
0179 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
0180 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
0181 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
0182 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
0183 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
0184 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
0185 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
0186 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
0187 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
0188 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
0189 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
0190 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
0191 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
0192 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
0193 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
0194 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
0195 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
0196 
0197 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
0198 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
0199 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
0200 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
0201 #endif
0202 };
0203 
0204 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
0205 
0206 static struct davinci_spi_platform_data dm365_spi0_pdata = {
0207     .version    = SPI_VERSION_1,
0208     .num_chipselect = 2,
0209     .dma_event_q    = EVENTQ_3,
0210     .prescaler_limit = 1,
0211 };
0212 
0213 static struct resource dm365_spi0_resources[] = {
0214     {
0215         .start = 0x01c66000,
0216         .end   = 0x01c667ff,
0217         .flags = IORESOURCE_MEM,
0218     },
0219     {
0220         .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
0221         .flags = IORESOURCE_IRQ,
0222     },
0223 };
0224 
0225 static struct platform_device dm365_spi0_device = {
0226     .name = "spi_davinci",
0227     .id = 0,
0228     .dev = {
0229         .dma_mask = &dm365_spi0_dma_mask,
0230         .coherent_dma_mask = DMA_BIT_MASK(32),
0231         .platform_data = &dm365_spi0_pdata,
0232     },
0233     .num_resources = ARRAY_SIZE(dm365_spi0_resources),
0234     .resource = dm365_spi0_resources,
0235 };
0236 
0237 void __init dm365_init_spi0(unsigned chipselect_mask,
0238         const struct spi_board_info *info, unsigned len)
0239 {
0240     davinci_cfg_reg(DM365_SPI0_SCLK);
0241     davinci_cfg_reg(DM365_SPI0_SDI);
0242     davinci_cfg_reg(DM365_SPI0_SDO);
0243 
0244     /* not all slaves will be wired up */
0245     if (chipselect_mask & BIT(0))
0246         davinci_cfg_reg(DM365_SPI0_SDENA0);
0247     if (chipselect_mask & BIT(1))
0248         davinci_cfg_reg(DM365_SPI0_SDENA1);
0249 
0250     spi_register_board_info(info, len);
0251 
0252     platform_device_register(&dm365_spi0_device);
0253 }
0254 
0255 static struct resource dm365_gpio_resources[] = {
0256     {   /* registers */
0257         .start  = DAVINCI_GPIO_BASE,
0258         .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
0259         .flags  = IORESOURCE_MEM,
0260     },
0261     {   /* interrupt */
0262         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
0263         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
0264         .flags  = IORESOURCE_IRQ,
0265     },
0266     {
0267         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
0268         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
0269         .flags  = IORESOURCE_IRQ,
0270     },
0271     {
0272         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
0273         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
0274         .flags  = IORESOURCE_IRQ,
0275     },
0276     {
0277         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
0278         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
0279         .flags  = IORESOURCE_IRQ,
0280     },
0281     {
0282         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
0283         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
0284         .flags  = IORESOURCE_IRQ,
0285     },
0286     {
0287         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
0288         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
0289         .flags  = IORESOURCE_IRQ,
0290     },
0291     {
0292         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
0293         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
0294         .flags  = IORESOURCE_IRQ,
0295     },
0296     {
0297         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
0298         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
0299         .flags  = IORESOURCE_IRQ,
0300     },
0301 };
0302 
0303 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
0304     .no_auto_base   = true,
0305     .base       = 0,
0306     .ngpio      = 104,
0307     .gpio_unbanked  = 8,
0308 };
0309 
0310 int __init dm365_gpio_register(void)
0311 {
0312     return davinci_gpio_register(dm365_gpio_resources,
0313                      ARRAY_SIZE(dm365_gpio_resources),
0314                      &dm365_gpio_platform_data);
0315 }
0316 
0317 static struct emac_platform_data dm365_emac_pdata = {
0318     .ctrl_reg_offset    = DM365_EMAC_CNTRL_OFFSET,
0319     .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
0320     .ctrl_ram_offset    = DM365_EMAC_CNTRL_RAM_OFFSET,
0321     .ctrl_ram_size      = DM365_EMAC_CNTRL_RAM_SIZE,
0322     .version        = EMAC_VERSION_2,
0323 };
0324 
0325 static struct resource dm365_emac_resources[] = {
0326     {
0327         .start  = DM365_EMAC_BASE,
0328         .end    = DM365_EMAC_BASE + SZ_16K - 1,
0329         .flags  = IORESOURCE_MEM,
0330     },
0331     {
0332         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
0333         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
0334         .flags  = IORESOURCE_IRQ,
0335     },
0336     {
0337         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
0338         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
0339         .flags  = IORESOURCE_IRQ,
0340     },
0341     {
0342         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
0343         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
0344         .flags  = IORESOURCE_IRQ,
0345     },
0346     {
0347         .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
0348         .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
0349         .flags  = IORESOURCE_IRQ,
0350     },
0351 };
0352 
0353 static struct platform_device dm365_emac_device = {
0354     .name       = "davinci_emac",
0355     .id     = 1,
0356     .dev = {
0357         .platform_data  = &dm365_emac_pdata,
0358     },
0359     .num_resources  = ARRAY_SIZE(dm365_emac_resources),
0360     .resource   = dm365_emac_resources,
0361 };
0362 
0363 static struct resource dm365_mdio_resources[] = {
0364     {
0365         .start  = DM365_EMAC_MDIO_BASE,
0366         .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
0367         .flags  = IORESOURCE_MEM,
0368     },
0369 };
0370 
0371 static struct platform_device dm365_mdio_device = {
0372     .name       = "davinci_mdio",
0373     .id     = 0,
0374     .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
0375     .resource   = dm365_mdio_resources,
0376 };
0377 
0378 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
0379     [IRQ_VDINT0]            = 2,
0380     [IRQ_VDINT1]            = 6,
0381     [IRQ_VDINT2]            = 6,
0382     [IRQ_HISTINT]           = 6,
0383     [IRQ_H3AINT]            = 6,
0384     [IRQ_PRVUINT]           = 6,
0385     [IRQ_RSZINT]            = 6,
0386     [IRQ_DM365_INSFINT]     = 7,
0387     [IRQ_VENCINT]           = 6,
0388     [IRQ_ASQINT]            = 6,
0389     [IRQ_IMXINT]            = 6,
0390     [IRQ_DM365_IMCOPINT]        = 4,
0391     [IRQ_USBINT]            = 4,
0392     [IRQ_DM365_RTOINT]      = 7,
0393     [IRQ_DM365_TINT5]       = 7,
0394     [IRQ_DM365_TINT6]       = 5,
0395     [IRQ_CCINT0]            = 5,
0396     [IRQ_CCERRINT]          = 5,
0397     [IRQ_TCERRINT0]         = 5,
0398     [IRQ_TCERRINT]          = 7,
0399     [IRQ_PSCIN]         = 4,
0400     [IRQ_DM365_SPINT2_1]        = 7,
0401     [IRQ_DM365_TINT7]       = 7,
0402     [IRQ_DM365_SDIOINT0]        = 7,
0403     [IRQ_MBXINT]            = 7,
0404     [IRQ_MBRINT]            = 7,
0405     [IRQ_MMCINT]            = 7,
0406     [IRQ_DM365_MMCINT1]     = 7,
0407     [IRQ_DM365_PWMINT3]     = 7,
0408     [IRQ_AEMIFINT]          = 2,
0409     [IRQ_DM365_SDIOINT1]        = 2,
0410     [IRQ_TINT0_TINT12]      = 7,
0411     [IRQ_TINT0_TINT34]      = 7,
0412     [IRQ_TINT1_TINT12]      = 7,
0413     [IRQ_TINT1_TINT34]      = 7,
0414     [IRQ_PWMINT0]           = 7,
0415     [IRQ_PWMINT1]           = 3,
0416     [IRQ_PWMINT2]           = 3,
0417     [IRQ_I2C]           = 3,
0418     [IRQ_UARTINT0]          = 3,
0419     [IRQ_UARTINT1]          = 3,
0420     [IRQ_DM365_RTCINT]      = 3,
0421     [IRQ_DM365_SPIINT0_0]       = 3,
0422     [IRQ_DM365_SPIINT3_0]       = 3,
0423     [IRQ_DM365_GPIO0]       = 3,
0424     [IRQ_DM365_GPIO1]       = 7,
0425     [IRQ_DM365_GPIO2]       = 4,
0426     [IRQ_DM365_GPIO3]       = 4,
0427     [IRQ_DM365_GPIO4]       = 7,
0428     [IRQ_DM365_GPIO5]       = 7,
0429     [IRQ_DM365_GPIO6]       = 7,
0430     [IRQ_DM365_GPIO7]       = 7,
0431     [IRQ_DM365_EMAC_RXTHRESH]   = 7,
0432     [IRQ_DM365_EMAC_RXPULSE]    = 7,
0433     [IRQ_DM365_EMAC_TXPULSE]    = 7,
0434     [IRQ_DM365_EMAC_MISCPULSE]  = 7,
0435     [IRQ_DM365_GPIO12]      = 7,
0436     [IRQ_DM365_GPIO13]      = 7,
0437     [IRQ_DM365_GPIO14]      = 7,
0438     [IRQ_DM365_GPIO15]      = 7,
0439     [IRQ_DM365_KEYINT]      = 7,
0440     [IRQ_DM365_TCERRINT2]       = 7,
0441     [IRQ_DM365_TCERRINT3]       = 7,
0442     [IRQ_DM365_EMUINT]      = 7,
0443 };
0444 
0445 /* Four Transfer Controllers on DM365 */
0446 static s8 dm365_queue_priority_mapping[][2] = {
0447     /* {event queue no, Priority} */
0448     {0, 7},
0449     {1, 7},
0450     {2, 7},
0451     {3, 0},
0452     {-1, -1},
0453 };
0454 
0455 static const struct dma_slave_map dm365_edma_map[] = {
0456     { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
0457     { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
0458     { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
0459     { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
0460     { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
0461     { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
0462     { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
0463     { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
0464     { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
0465     { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
0466     { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
0467     { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
0468     { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
0469     { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
0470     { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
0471     { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
0472 };
0473 
0474 static struct edma_soc_info dm365_edma_pdata = {
0475     .queue_priority_mapping = dm365_queue_priority_mapping,
0476     .default_queue      = EVENTQ_3,
0477     .slave_map      = dm365_edma_map,
0478     .slavecnt       = ARRAY_SIZE(dm365_edma_map),
0479 };
0480 
0481 static struct resource edma_resources[] = {
0482     {
0483         .name   = "edma3_cc",
0484         .start  = 0x01c00000,
0485         .end    = 0x01c00000 + SZ_64K - 1,
0486         .flags  = IORESOURCE_MEM,
0487     },
0488     {
0489         .name   = "edma3_tc0",
0490         .start  = 0x01c10000,
0491         .end    = 0x01c10000 + SZ_1K - 1,
0492         .flags  = IORESOURCE_MEM,
0493     },
0494     {
0495         .name   = "edma3_tc1",
0496         .start  = 0x01c10400,
0497         .end    = 0x01c10400 + SZ_1K - 1,
0498         .flags  = IORESOURCE_MEM,
0499     },
0500     {
0501         .name   = "edma3_tc2",
0502         .start  = 0x01c10800,
0503         .end    = 0x01c10800 + SZ_1K - 1,
0504         .flags  = IORESOURCE_MEM,
0505     },
0506     {
0507         .name   = "edma3_tc3",
0508         .start  = 0x01c10c00,
0509         .end    = 0x01c10c00 + SZ_1K - 1,
0510         .flags  = IORESOURCE_MEM,
0511     },
0512     {
0513         .name   = "edma3_ccint",
0514         .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
0515         .flags  = IORESOURCE_IRQ,
0516     },
0517     {
0518         .name   = "edma3_ccerrint",
0519         .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
0520         .flags  = IORESOURCE_IRQ,
0521     },
0522     /* not using TC*_ERR */
0523 };
0524 
0525 static const struct platform_device_info dm365_edma_device __initconst = {
0526     .name       = "edma",
0527     .id     = 0,
0528     .dma_mask   = DMA_BIT_MASK(32),
0529     .res        = edma_resources,
0530     .num_res    = ARRAY_SIZE(edma_resources),
0531     .data       = &dm365_edma_pdata,
0532     .size_data  = sizeof(dm365_edma_pdata),
0533 };
0534 
0535 static struct resource dm365_asp_resources[] = {
0536     {
0537         .name   = "mpu",
0538         .start  = DAVINCI_DM365_ASP0_BASE,
0539         .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
0540         .flags  = IORESOURCE_MEM,
0541     },
0542     {
0543         .start  = DAVINCI_DMA_ASP0_TX,
0544         .end    = DAVINCI_DMA_ASP0_TX,
0545         .flags  = IORESOURCE_DMA,
0546     },
0547     {
0548         .start  = DAVINCI_DMA_ASP0_RX,
0549         .end    = DAVINCI_DMA_ASP0_RX,
0550         .flags  = IORESOURCE_DMA,
0551     },
0552 };
0553 
0554 static struct platform_device dm365_asp_device = {
0555     .name       = "davinci-mcbsp",
0556     .id     = -1,
0557     .num_resources  = ARRAY_SIZE(dm365_asp_resources),
0558     .resource   = dm365_asp_resources,
0559 };
0560 
0561 static struct resource dm365_vc_resources[] = {
0562     {
0563         .start  = DAVINCI_DM365_VC_BASE,
0564         .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
0565         .flags  = IORESOURCE_MEM,
0566     },
0567     {
0568         .start  = DAVINCI_DMA_VC_TX,
0569         .end    = DAVINCI_DMA_VC_TX,
0570         .flags  = IORESOURCE_DMA,
0571     },
0572     {
0573         .start  = DAVINCI_DMA_VC_RX,
0574         .end    = DAVINCI_DMA_VC_RX,
0575         .flags  = IORESOURCE_DMA,
0576     },
0577 };
0578 
0579 static struct platform_device dm365_vc_device = {
0580     .name       = "davinci_voicecodec",
0581     .id     = -1,
0582     .num_resources  = ARRAY_SIZE(dm365_vc_resources),
0583     .resource   = dm365_vc_resources,
0584 };
0585 
0586 static struct resource dm365_rtc_resources[] = {
0587     {
0588         .start = DM365_RTC_BASE,
0589         .end = DM365_RTC_BASE + SZ_1K - 1,
0590         .flags = IORESOURCE_MEM,
0591     },
0592     {
0593         .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
0594         .flags = IORESOURCE_IRQ,
0595     },
0596 };
0597 
0598 static struct platform_device dm365_rtc_device = {
0599     .name = "rtc_davinci",
0600     .id = 0,
0601     .num_resources = ARRAY_SIZE(dm365_rtc_resources),
0602     .resource = dm365_rtc_resources,
0603 };
0604 
0605 static struct map_desc dm365_io_desc[] = {
0606     {
0607         .virtual    = IO_VIRT,
0608         .pfn        = __phys_to_pfn(IO_PHYS),
0609         .length     = IO_SIZE,
0610         .type       = MT_DEVICE
0611     },
0612 };
0613 
0614 static struct resource dm365_ks_resources[] = {
0615     {
0616         /* registers */
0617         .start = DM365_KEYSCAN_BASE,
0618         .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
0619         .flags = IORESOURCE_MEM,
0620     },
0621     {
0622         /* interrupt */
0623         .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
0624         .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
0625         .flags = IORESOURCE_IRQ,
0626     },
0627 };
0628 
0629 static struct platform_device dm365_ks_device = {
0630     .name       = "davinci_keyscan",
0631     .id     = 0,
0632     .num_resources  = ARRAY_SIZE(dm365_ks_resources),
0633     .resource   = dm365_ks_resources,
0634 };
0635 
0636 /* Contents of JTAG ID register used to identify exact cpu type */
0637 static struct davinci_id dm365_ids[] = {
0638     {
0639         .variant    = 0x0,
0640         .part_no    = 0xb83e,
0641         .manufacturer   = 0x017,
0642         .cpu_id     = DAVINCI_CPU_ID_DM365,
0643         .name       = "dm365_rev1.1",
0644     },
0645     {
0646         .variant    = 0x8,
0647         .part_no    = 0xb83e,
0648         .manufacturer   = 0x017,
0649         .cpu_id     = DAVINCI_CPU_ID_DM365,
0650         .name       = "dm365_rev1.2",
0651     },
0652 };
0653 
0654 /*
0655  * Bottom half of timer0 is used for clockevent, top half is used for
0656  * clocksource.
0657  */
0658 static const struct davinci_timer_cfg dm365_timer_cfg = {
0659     .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
0660     .irq = {
0661         DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
0662         DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
0663     },
0664 };
0665 
0666 #define DM365_UART1_BASE    (IO_PHYS + 0x106000)
0667 
0668 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
0669     {
0670         .mapbase    = DAVINCI_UART0_BASE,
0671         .irq        = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
0672         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
0673                   UPF_IOREMAP,
0674         .iotype     = UPIO_MEM,
0675         .regshift   = 2,
0676     },
0677     {
0678         .flags  = 0,
0679     }
0680 };
0681 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
0682     {
0683         .mapbase    = DM365_UART1_BASE,
0684         .irq        = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
0685         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
0686                   UPF_IOREMAP,
0687         .iotype     = UPIO_MEM,
0688         .regshift   = 2,
0689     },
0690     {
0691         .flags  = 0,
0692     }
0693 };
0694 
0695 struct platform_device dm365_serial_device[] = {
0696     {
0697         .name           = "serial8250",
0698         .id         = PLAT8250_DEV_PLATFORM,
0699         .dev            = {
0700             .platform_data  = dm365_serial0_platform_data,
0701         }
0702     },
0703     {
0704         .name           = "serial8250",
0705         .id         = PLAT8250_DEV_PLATFORM1,
0706         .dev            = {
0707             .platform_data  = dm365_serial1_platform_data,
0708         }
0709     },
0710     {
0711     }
0712 };
0713 
0714 static const struct davinci_soc_info davinci_soc_info_dm365 = {
0715     .io_desc        = dm365_io_desc,
0716     .io_desc_num        = ARRAY_SIZE(dm365_io_desc),
0717     .jtag_id_reg        = 0x01c40028,
0718     .ids            = dm365_ids,
0719     .ids_num        = ARRAY_SIZE(dm365_ids),
0720     .pinmux_base        = DAVINCI_SYSTEM_MODULE_BASE,
0721     .pinmux_pins        = dm365_pins,
0722     .pinmux_pins_num    = ARRAY_SIZE(dm365_pins),
0723     .emac_pdata     = &dm365_emac_pdata,
0724     .sram_dma       = 0x00010000,
0725     .sram_len       = SZ_32K,
0726 };
0727 
0728 void __init dm365_init_asp(void)
0729 {
0730     davinci_cfg_reg(DM365_MCBSP0_BDX);
0731     davinci_cfg_reg(DM365_MCBSP0_X);
0732     davinci_cfg_reg(DM365_MCBSP0_BFSX);
0733     davinci_cfg_reg(DM365_MCBSP0_BDR);
0734     davinci_cfg_reg(DM365_MCBSP0_R);
0735     davinci_cfg_reg(DM365_MCBSP0_BFSR);
0736     davinci_cfg_reg(DM365_EVT2_ASP_TX);
0737     davinci_cfg_reg(DM365_EVT3_ASP_RX);
0738     platform_device_register(&dm365_asp_device);
0739 }
0740 
0741 void __init dm365_init_vc(void)
0742 {
0743     davinci_cfg_reg(DM365_EVT2_VC_TX);
0744     davinci_cfg_reg(DM365_EVT3_VC_RX);
0745     platform_device_register(&dm365_vc_device);
0746 }
0747 
0748 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
0749 {
0750     dm365_ks_device.dev.platform_data = pdata;
0751     platform_device_register(&dm365_ks_device);
0752 }
0753 
0754 void __init dm365_init_rtc(void)
0755 {
0756     davinci_cfg_reg(DM365_INT_PRTCSS);
0757     platform_device_register(&dm365_rtc_device);
0758 }
0759 
0760 void __init dm365_init(void)
0761 {
0762     davinci_common_init(&davinci_soc_info_dm365);
0763     davinci_map_sysmod();
0764 }
0765 
0766 void __init dm365_init_time(void)
0767 {
0768     void __iomem *pll1, *pll2, *psc;
0769     struct clk *clk;
0770     int rv;
0771 
0772     clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
0773 
0774     pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
0775     dm365_pll1_init(NULL, pll1, NULL);
0776 
0777     pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
0778     dm365_pll2_init(NULL, pll2, NULL);
0779 
0780     psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
0781     dm365_psc_init(NULL, psc);
0782 
0783     clk = clk_get(NULL, "timer0");
0784     if (WARN_ON(IS_ERR(clk))) {
0785         pr_err("Unable to get the timer clock\n");
0786         return;
0787     }
0788 
0789     rv = davinci_timer_register(clk, &dm365_timer_cfg);
0790     WARN(rv, "Unable to register the timer: %d\n", rv);
0791 }
0792 
0793 void __init dm365_register_clocks(void)
0794 {
0795     /* all clocks are currently registered in dm365_init_time() */
0796 }
0797 
0798 static struct resource dm365_vpss_resources[] = {
0799     {
0800         /* VPSS ISP5 Base address */
0801         .name           = "isp5",
0802         .start          = 0x01c70000,
0803         .end            = 0x01c70000 + 0xff,
0804         .flags          = IORESOURCE_MEM,
0805     },
0806     {
0807         /* VPSS CLK Base address */
0808         .name           = "vpss",
0809         .start          = 0x01c70200,
0810         .end            = 0x01c70200 + 0xff,
0811         .flags          = IORESOURCE_MEM,
0812     },
0813 };
0814 
0815 static struct platform_device dm365_vpss_device = {
0816        .name                   = "vpss",
0817        .id                     = -1,
0818        .dev.platform_data      = "dm365_vpss",
0819        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
0820        .resource               = dm365_vpss_resources,
0821 };
0822 
0823 static struct resource vpfe_resources[] = {
0824     {
0825         .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
0826         .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
0827         .flags          = IORESOURCE_IRQ,
0828     },
0829     {
0830         .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
0831         .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
0832         .flags          = IORESOURCE_IRQ,
0833     },
0834 };
0835 
0836 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
0837 static struct platform_device vpfe_capture_dev = {
0838     .name           = CAPTURE_DRV_NAME,
0839     .id             = -1,
0840     .num_resources  = ARRAY_SIZE(vpfe_resources),
0841     .resource       = vpfe_resources,
0842     .dev = {
0843         .dma_mask               = &vpfe_capture_dma_mask,
0844         .coherent_dma_mask      = DMA_BIT_MASK(32),
0845     },
0846 };
0847 
0848 static void dm365_isif_setup_pinmux(void)
0849 {
0850     davinci_cfg_reg(DM365_VIN_CAM_WEN);
0851     davinci_cfg_reg(DM365_VIN_CAM_VD);
0852     davinci_cfg_reg(DM365_VIN_CAM_HD);
0853     davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
0854     davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
0855 }
0856 
0857 static struct resource isif_resource[] = {
0858     /* ISIF Base address */
0859     {
0860         .start          = 0x01c71000,
0861         .end            = 0x01c71000 + 0x1ff,
0862         .flags          = IORESOURCE_MEM,
0863     },
0864     /* ISIF Linearization table 0 */
0865     {
0866         .start          = 0x1C7C000,
0867         .end            = 0x1C7C000 + 0x2ff,
0868         .flags          = IORESOURCE_MEM,
0869     },
0870     /* ISIF Linearization table 1 */
0871     {
0872         .start          = 0x1C7C400,
0873         .end            = 0x1C7C400 + 0x2ff,
0874         .flags          = IORESOURCE_MEM,
0875     },
0876 };
0877 static struct platform_device dm365_isif_dev = {
0878     .name           = "isif",
0879     .id             = -1,
0880     .num_resources  = ARRAY_SIZE(isif_resource),
0881     .resource       = isif_resource,
0882     .dev = {
0883         .dma_mask               = &vpfe_capture_dma_mask,
0884         .coherent_dma_mask      = DMA_BIT_MASK(32),
0885         .platform_data      = dm365_isif_setup_pinmux,
0886     },
0887 };
0888 
0889 static struct resource dm365_osd_resources[] = {
0890     {
0891         .start = DM365_OSD_BASE,
0892         .end   = DM365_OSD_BASE + 0xff,
0893         .flags = IORESOURCE_MEM,
0894     },
0895 };
0896 
0897 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
0898 
0899 static struct platform_device dm365_osd_dev = {
0900     .name       = DM365_VPBE_OSD_SUBDEV_NAME,
0901     .id     = -1,
0902     .num_resources  = ARRAY_SIZE(dm365_osd_resources),
0903     .resource   = dm365_osd_resources,
0904     .dev        = {
0905         .dma_mask       = &dm365_video_dma_mask,
0906         .coherent_dma_mask  = DMA_BIT_MASK(32),
0907     },
0908 };
0909 
0910 static struct resource dm365_venc_resources[] = {
0911     {
0912         .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
0913         .end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
0914         .flags = IORESOURCE_IRQ,
0915     },
0916     /* venc registers io space */
0917     {
0918         .start = DM365_VENC_BASE,
0919         .end   = DM365_VENC_BASE + 0x177,
0920         .flags = IORESOURCE_MEM,
0921     },
0922     /* vdaccfg registers io space */
0923     {
0924         .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
0925         .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
0926         .flags = IORESOURCE_MEM,
0927     },
0928 };
0929 
0930 static struct resource dm365_v4l2_disp_resources[] = {
0931     {
0932         .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
0933         .end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
0934         .flags = IORESOURCE_IRQ,
0935     },
0936     /* venc registers io space */
0937     {
0938         .start = DM365_VENC_BASE,
0939         .end   = DM365_VENC_BASE + 0x177,
0940         .flags = IORESOURCE_MEM,
0941     },
0942 };
0943 
0944 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
0945 {
0946     switch (if_type) {
0947     case MEDIA_BUS_FMT_SGRBG8_1X8:
0948         davinci_cfg_reg(DM365_VOUT_FIELD_G81);
0949         davinci_cfg_reg(DM365_VOUT_COUTL_EN);
0950         davinci_cfg_reg(DM365_VOUT_COUTH_EN);
0951         break;
0952     case MEDIA_BUS_FMT_YUYV10_1X20:
0953         if (field)
0954             davinci_cfg_reg(DM365_VOUT_FIELD);
0955         else
0956             davinci_cfg_reg(DM365_VOUT_FIELD_G81);
0957         davinci_cfg_reg(DM365_VOUT_COUTL_EN);
0958         davinci_cfg_reg(DM365_VOUT_COUTH_EN);
0959         break;
0960     default:
0961         return -EINVAL;
0962     }
0963 
0964     return 0;
0965 }
0966 
0967 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
0968                   unsigned int pclock)
0969 {
0970     void __iomem *vpss_clkctl_reg;
0971     u32 val;
0972 
0973     vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
0974 
0975     switch (type) {
0976     case VPBE_ENC_STD:
0977         val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
0978         break;
0979     case VPBE_ENC_DV_TIMINGS:
0980         if (pclock <= 27000000) {
0981             val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
0982         } else {
0983             /* set sysclk4 to output 74.25 MHz from pll1 */
0984             val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
0985                   VPSS_VENCCLKEN_ENABLE;
0986         }
0987         break;
0988     default:
0989         return -EINVAL;
0990     }
0991     writel(val, vpss_clkctl_reg);
0992 
0993     return 0;
0994 }
0995 
0996 static struct platform_device dm365_vpbe_display = {
0997     .name       = "vpbe-v4l2",
0998     .id     = -1,
0999     .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
1000     .resource   = dm365_v4l2_disp_resources,
1001     .dev        = {
1002         .dma_mask       = &dm365_video_dma_mask,
1003         .coherent_dma_mask  = DMA_BIT_MASK(32),
1004     },
1005 };
1006 
1007 static struct venc_platform_data dm365_venc_pdata = {
1008     .setup_pinmux   = dm365_vpbe_setup_pinmux,
1009     .setup_clock    = dm365_venc_setup_clock,
1010 };
1011 
1012 static struct platform_device dm365_venc_dev = {
1013     .name       = DM365_VPBE_VENC_SUBDEV_NAME,
1014     .id     = -1,
1015     .num_resources  = ARRAY_SIZE(dm365_venc_resources),
1016     .resource   = dm365_venc_resources,
1017     .dev        = {
1018         .dma_mask       = &dm365_video_dma_mask,
1019         .coherent_dma_mask  = DMA_BIT_MASK(32),
1020         .platform_data      = (void *)&dm365_venc_pdata,
1021     },
1022 };
1023 
1024 static struct platform_device dm365_vpbe_dev = {
1025     .name       = "vpbe_controller",
1026     .id     = -1,
1027     .dev        = {
1028         .dma_mask       = &dm365_video_dma_mask,
1029         .coherent_dma_mask  = DMA_BIT_MASK(32),
1030     },
1031 };
1032 
1033 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1034                 struct vpbe_config *vpbe_cfg)
1035 {
1036     if (vpfe_cfg || vpbe_cfg)
1037         platform_device_register(&dm365_vpss_device);
1038 
1039     if (vpfe_cfg) {
1040         vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1041         platform_device_register(&dm365_isif_dev);
1042         platform_device_register(&vpfe_capture_dev);
1043     }
1044     if (vpbe_cfg) {
1045         dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1046         platform_device_register(&dm365_osd_dev);
1047         platform_device_register(&dm365_venc_dev);
1048         platform_device_register(&dm365_vpbe_dev);
1049         platform_device_register(&dm365_vpbe_display);
1050     }
1051 
1052     return 0;
1053 }
1054 
1055 static const struct davinci_aintc_config dm365_aintc_config = {
1056     .reg = {
1057         .start      = DAVINCI_ARM_INTC_BASE,
1058         .end        = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
1059         .flags      = IORESOURCE_MEM,
1060     },
1061     .num_irqs       = 64,
1062     .prios          = dm365_default_priorities,
1063 };
1064 
1065 void __init dm365_init_irq(void)
1066 {
1067     davinci_aintc_init(&dm365_aintc_config);
1068 }
1069 
1070 static int __init dm365_init_devices(void)
1071 {
1072     struct platform_device *edma_pdev;
1073     int ret = 0;
1074 
1075     if (!cpu_is_davinci_dm365())
1076         return 0;
1077 
1078     davinci_cfg_reg(DM365_INT_EDMA_CC);
1079     edma_pdev = platform_device_register_full(&dm365_edma_device);
1080     if (IS_ERR(edma_pdev)) {
1081         pr_warn("%s: Failed to register eDMA\n", __func__);
1082         return PTR_ERR(edma_pdev);
1083     }
1084 
1085     platform_device_register(&dm365_mdio_device);
1086     platform_device_register(&dm365_emac_device);
1087 
1088     ret = davinci_init_wdt();
1089     if (ret)
1090         pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1091 
1092     return ret;
1093 }
1094 postcore_initcall(dm365_init_devices);
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