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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * TI DaVinci DM355 chip specific setup
0004  *
0005  * Author: Kevin Hilman, Deep Root Systems, LLC
0006  *
0007  * 2007 (c) Deep Root Systems, LLC.
0008  */
0009 
0010 #include <linux/clk-provider.h>
0011 #include <linux/clk/davinci.h>
0012 #include <linux/clkdev.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/dmaengine.h>
0015 #include <linux/init.h>
0016 #include <linux/io.h>
0017 #include <linux/irqchip/irq-davinci-aintc.h>
0018 #include <linux/platform_data/edma.h>
0019 #include <linux/platform_data/gpio-davinci.h>
0020 #include <linux/platform_data/spi-davinci.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/serial_8250.h>
0023 #include <linux/spi/spi.h>
0024 
0025 #include <clocksource/timer-davinci.h>
0026 
0027 #include <asm/mach/map.h>
0028 
0029 #include "common.h"
0030 #include "cputype.h"
0031 #include "serial.h"
0032 #include "asp.h"
0033 #include "davinci.h"
0034 #include "irqs.h"
0035 #include "mux.h"
0036 
0037 #define DM355_UART2_BASE    (IO_PHYS + 0x206000)
0038 #define DM355_OSD_BASE      (IO_PHYS + 0x70200)
0039 #define DM355_VENC_BASE     (IO_PHYS + 0x70400)
0040 
0041 /*
0042  * Device specific clocks
0043  */
0044 #define DM355_REF_FREQ      24000000    /* 24 or 36 MHz */
0045 
0046 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
0047 
0048 static struct resource dm355_spi0_resources[] = {
0049     {
0050         .start = 0x01c66000,
0051         .end   = 0x01c667ff,
0052         .flags = IORESOURCE_MEM,
0053     },
0054     {
0055         .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
0056         .flags = IORESOURCE_IRQ,
0057     },
0058 };
0059 
0060 static struct davinci_spi_platform_data dm355_spi0_pdata = {
0061     .version    = SPI_VERSION_1,
0062     .num_chipselect = 2,
0063     .cshold_bug = true,
0064     .dma_event_q    = EVENTQ_1,
0065     .prescaler_limit = 1,
0066 };
0067 static struct platform_device dm355_spi0_device = {
0068     .name = "spi_davinci",
0069     .id = 0,
0070     .dev = {
0071         .dma_mask = &dm355_spi0_dma_mask,
0072         .coherent_dma_mask = DMA_BIT_MASK(32),
0073         .platform_data = &dm355_spi0_pdata,
0074     },
0075     .num_resources = ARRAY_SIZE(dm355_spi0_resources),
0076     .resource = dm355_spi0_resources,
0077 };
0078 
0079 void __init dm355_init_spi0(unsigned chipselect_mask,
0080         const struct spi_board_info *info, unsigned len)
0081 {
0082     /* for now, assume we need MISO */
0083     davinci_cfg_reg(DM355_SPI0_SDI);
0084 
0085     /* not all slaves will be wired up */
0086     if (chipselect_mask & BIT(0))
0087         davinci_cfg_reg(DM355_SPI0_SDENA0);
0088     if (chipselect_mask & BIT(1))
0089         davinci_cfg_reg(DM355_SPI0_SDENA1);
0090 
0091     spi_register_board_info(info, len);
0092 
0093     platform_device_register(&dm355_spi0_device);
0094 }
0095 
0096 /*----------------------------------------------------------------------*/
0097 
0098 #define INTMUX      0x18
0099 #define EVTMUX      0x1c
0100 
0101 /*
0102  * Device specific mux setup
0103  *
0104  *  soc description mux  mode   mode  mux    dbg
0105  *              reg  offset mask  mode
0106  */
0107 static const struct mux_config dm355_pins[] = {
0108 #ifdef CONFIG_DAVINCI_MUX
0109 MUX_CFG(DM355,  MMCSD0,     4,   2,     1,    0,     false)
0110 
0111 MUX_CFG(DM355,  SD1_CLK,    3,   6,     1,    1,     false)
0112 MUX_CFG(DM355,  SD1_CMD,    3,   7,     1,    1,     false)
0113 MUX_CFG(DM355,  SD1_DATA3,  3,   8,     3,    1,     false)
0114 MUX_CFG(DM355,  SD1_DATA2,  3,   10,    3,    1,     false)
0115 MUX_CFG(DM355,  SD1_DATA1,  3,   12,    3,    1,     false)
0116 MUX_CFG(DM355,  SD1_DATA0,  3,   14,    3,    1,     false)
0117 
0118 MUX_CFG(DM355,  I2C_SDA,    3,   19,    1,    1,     false)
0119 MUX_CFG(DM355,  I2C_SCL,    3,   20,    1,    1,     false)
0120 
0121 MUX_CFG(DM355,  MCBSP0_BDX, 3,   0,     1,    1,     false)
0122 MUX_CFG(DM355,  MCBSP0_X,   3,   1,     1,    1,     false)
0123 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
0124 MUX_CFG(DM355,  MCBSP0_BDR, 3,   3,     1,    1,     false)
0125 MUX_CFG(DM355,  MCBSP0_R,   3,   4,     1,    1,     false)
0126 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
0127 
0128 MUX_CFG(DM355,  SPI0_SDI,   4,   1,     1,    0,     false)
0129 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
0130 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
0131 
0132 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
0133 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
0134 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
0135 
0136 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
0137 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
0138 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
0139 
0140 MUX_CFG(DM355,  VOUT_FIELD, 1,   18,    3,    1,     false)
0141 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
0142 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
0143 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
0144 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
0145 
0146 MUX_CFG(DM355,  VIN_PCLK,   0,   14,    1,    1,     false)
0147 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
0148 MUX_CFG(DM355,  VIN_CAM_VD, 0,   12,    1,    1,     false)
0149 MUX_CFG(DM355,  VIN_CAM_HD, 0,   11,    1,    1,     false)
0150 MUX_CFG(DM355,  VIN_YIN_EN, 0,   10,    1,    1,     false)
0151 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
0152 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
0153 #endif
0154 };
0155 
0156 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
0157     [IRQ_DM355_CCDC_VDINT0]     = 2,
0158     [IRQ_DM355_CCDC_VDINT1]     = 6,
0159     [IRQ_DM355_CCDC_VDINT2]     = 6,
0160     [IRQ_DM355_IPIPE_HST]       = 6,
0161     [IRQ_DM355_H3AINT]      = 6,
0162     [IRQ_DM355_IPIPE_SDR]       = 6,
0163     [IRQ_DM355_IPIPEIFINT]      = 6,
0164     [IRQ_DM355_OSDINT]      = 7,
0165     [IRQ_DM355_VENCINT]     = 6,
0166     [IRQ_ASQINT]            = 6,
0167     [IRQ_IMXINT]            = 6,
0168     [IRQ_USBINT]            = 4,
0169     [IRQ_DM355_RTOINT]      = 4,
0170     [IRQ_DM355_UARTINT2]        = 7,
0171     [IRQ_DM355_TINT6]       = 7,
0172     [IRQ_CCINT0]            = 5,    /* dma */
0173     [IRQ_CCERRINT]          = 5,    /* dma */
0174     [IRQ_TCERRINT0]         = 5,    /* dma */
0175     [IRQ_TCERRINT]          = 5,    /* dma */
0176     [IRQ_DM355_SPINT2_1]        = 7,
0177     [IRQ_DM355_TINT7]       = 4,
0178     [IRQ_DM355_SDIOINT0]        = 7,
0179     [IRQ_MBXINT]            = 7,
0180     [IRQ_MBRINT]            = 7,
0181     [IRQ_MMCINT]            = 7,
0182     [IRQ_DM355_MMCINT1]     = 7,
0183     [IRQ_DM355_PWMINT3]     = 7,
0184     [IRQ_DDRINT]            = 7,
0185     [IRQ_AEMIFINT]          = 7,
0186     [IRQ_DM355_SDIOINT1]        = 4,
0187     [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
0188     [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
0189     [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
0190     [IRQ_TINT1_TINT34]      = 7,    /* system tick */
0191     [IRQ_PWMINT0]           = 7,
0192     [IRQ_PWMINT1]           = 7,
0193     [IRQ_PWMINT2]           = 7,
0194     [IRQ_I2C]           = 3,
0195     [IRQ_UARTINT0]          = 3,
0196     [IRQ_UARTINT1]          = 3,
0197     [IRQ_DM355_SPINT0_0]        = 3,
0198     [IRQ_DM355_SPINT0_1]        = 3,
0199     [IRQ_DM355_GPIO0]       = 3,
0200     [IRQ_DM355_GPIO1]       = 7,
0201     [IRQ_DM355_GPIO2]       = 4,
0202     [IRQ_DM355_GPIO3]       = 4,
0203     [IRQ_DM355_GPIO4]       = 7,
0204     [IRQ_DM355_GPIO5]       = 7,
0205     [IRQ_DM355_GPIO6]       = 7,
0206     [IRQ_DM355_GPIO7]       = 7,
0207     [IRQ_DM355_GPIO8]       = 7,
0208     [IRQ_DM355_GPIO9]       = 7,
0209     [IRQ_DM355_GPIOBNK0]        = 7,
0210     [IRQ_DM355_GPIOBNK1]        = 7,
0211     [IRQ_DM355_GPIOBNK2]        = 7,
0212     [IRQ_DM355_GPIOBNK3]        = 7,
0213     [IRQ_DM355_GPIOBNK4]        = 7,
0214     [IRQ_DM355_GPIOBNK5]        = 7,
0215     [IRQ_DM355_GPIOBNK6]        = 7,
0216     [IRQ_COMMTX]            = 7,
0217     [IRQ_COMMRX]            = 7,
0218     [IRQ_EMUINT]            = 7,
0219 };
0220 
0221 /*----------------------------------------------------------------------*/
0222 
0223 static s8 queue_priority_mapping[][2] = {
0224     /* {event queue no, Priority} */
0225     {0, 3},
0226     {1, 7},
0227     {-1, -1},
0228 };
0229 
0230 static const struct dma_slave_map dm355_edma_map[] = {
0231     { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
0232     { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
0233     { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
0234     { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
0235     { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
0236     { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
0237     { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
0238     { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
0239     { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
0240     { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
0241     { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
0242     { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
0243     { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
0244     { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
0245 };
0246 
0247 static struct edma_soc_info dm355_edma_pdata = {
0248     .queue_priority_mapping = queue_priority_mapping,
0249     .default_queue      = EVENTQ_1,
0250     .slave_map      = dm355_edma_map,
0251     .slavecnt       = ARRAY_SIZE(dm355_edma_map),
0252 };
0253 
0254 static struct resource edma_resources[] = {
0255     {
0256         .name   = "edma3_cc",
0257         .start  = 0x01c00000,
0258         .end    = 0x01c00000 + SZ_64K - 1,
0259         .flags  = IORESOURCE_MEM,
0260     },
0261     {
0262         .name   = "edma3_tc0",
0263         .start  = 0x01c10000,
0264         .end    = 0x01c10000 + SZ_1K - 1,
0265         .flags  = IORESOURCE_MEM,
0266     },
0267     {
0268         .name   = "edma3_tc1",
0269         .start  = 0x01c10400,
0270         .end    = 0x01c10400 + SZ_1K - 1,
0271         .flags  = IORESOURCE_MEM,
0272     },
0273     {
0274         .name   = "edma3_ccint",
0275         .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
0276         .flags  = IORESOURCE_IRQ,
0277     },
0278     {
0279         .name   = "edma3_ccerrint",
0280         .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
0281         .flags  = IORESOURCE_IRQ,
0282     },
0283     /* not using (or muxing) TC*_ERR */
0284 };
0285 
0286 static const struct platform_device_info dm355_edma_device __initconst = {
0287     .name       = "edma",
0288     .id     = 0,
0289     .dma_mask   = DMA_BIT_MASK(32),
0290     .res        = edma_resources,
0291     .num_res    = ARRAY_SIZE(edma_resources),
0292     .data       = &dm355_edma_pdata,
0293     .size_data  = sizeof(dm355_edma_pdata),
0294 };
0295 
0296 static struct resource dm355_asp1_resources[] = {
0297     {
0298         .name   = "mpu",
0299         .start  = DAVINCI_ASP1_BASE,
0300         .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
0301         .flags  = IORESOURCE_MEM,
0302     },
0303     {
0304         .start  = DAVINCI_DMA_ASP1_TX,
0305         .end    = DAVINCI_DMA_ASP1_TX,
0306         .flags  = IORESOURCE_DMA,
0307     },
0308     {
0309         .start  = DAVINCI_DMA_ASP1_RX,
0310         .end    = DAVINCI_DMA_ASP1_RX,
0311         .flags  = IORESOURCE_DMA,
0312     },
0313 };
0314 
0315 static struct platform_device dm355_asp1_device = {
0316     .name       = "davinci-mcbsp",
0317     .id     = 1,
0318     .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
0319     .resource   = dm355_asp1_resources,
0320 };
0321 
0322 static void dm355_ccdc_setup_pinmux(void)
0323 {
0324     davinci_cfg_reg(DM355_VIN_PCLK);
0325     davinci_cfg_reg(DM355_VIN_CAM_WEN);
0326     davinci_cfg_reg(DM355_VIN_CAM_VD);
0327     davinci_cfg_reg(DM355_VIN_CAM_HD);
0328     davinci_cfg_reg(DM355_VIN_YIN_EN);
0329     davinci_cfg_reg(DM355_VIN_CINL_EN);
0330     davinci_cfg_reg(DM355_VIN_CINH_EN);
0331 }
0332 
0333 static struct resource dm355_vpss_resources[] = {
0334     {
0335         /* VPSS BL Base address */
0336         .name       = "vpss",
0337         .start          = 0x01c70800,
0338         .end            = 0x01c70800 + 0xff,
0339         .flags          = IORESOURCE_MEM,
0340     },
0341     {
0342         /* VPSS CLK Base address */
0343         .name       = "vpss",
0344         .start          = 0x01c70000,
0345         .end            = 0x01c70000 + 0xf,
0346         .flags          = IORESOURCE_MEM,
0347     },
0348 };
0349 
0350 static struct platform_device dm355_vpss_device = {
0351     .name           = "vpss",
0352     .id         = -1,
0353     .dev.platform_data  = "dm355_vpss",
0354     .num_resources      = ARRAY_SIZE(dm355_vpss_resources),
0355     .resource       = dm355_vpss_resources,
0356 };
0357 
0358 static struct resource vpfe_resources[] = {
0359     {
0360         .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
0361         .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
0362         .flags          = IORESOURCE_IRQ,
0363     },
0364     {
0365         .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
0366         .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
0367         .flags          = IORESOURCE_IRQ,
0368     },
0369 };
0370 
0371 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
0372 static struct resource dm355_ccdc_resource[] = {
0373     /* CCDC Base address */
0374     {
0375         .flags          = IORESOURCE_MEM,
0376         .start          = 0x01c70600,
0377         .end            = 0x01c70600 + 0x1ff,
0378     },
0379 };
0380 static struct platform_device dm355_ccdc_dev = {
0381     .name           = "dm355_ccdc",
0382     .id             = -1,
0383     .num_resources  = ARRAY_SIZE(dm355_ccdc_resource),
0384     .resource       = dm355_ccdc_resource,
0385     .dev = {
0386         .dma_mask               = &vpfe_capture_dma_mask,
0387         .coherent_dma_mask      = DMA_BIT_MASK(32),
0388         .platform_data      = dm355_ccdc_setup_pinmux,
0389     },
0390 };
0391 
0392 static struct platform_device vpfe_capture_dev = {
0393     .name       = CAPTURE_DRV_NAME,
0394     .id     = -1,
0395     .num_resources  = ARRAY_SIZE(vpfe_resources),
0396     .resource   = vpfe_resources,
0397     .dev = {
0398         .dma_mask       = &vpfe_capture_dma_mask,
0399         .coherent_dma_mask  = DMA_BIT_MASK(32),
0400     },
0401 };
0402 
0403 static struct resource dm355_osd_resources[] = {
0404     {
0405         .start  = DM355_OSD_BASE,
0406         .end    = DM355_OSD_BASE + 0x17f,
0407         .flags  = IORESOURCE_MEM,
0408     },
0409 };
0410 
0411 static struct platform_device dm355_osd_dev = {
0412     .name       = DM355_VPBE_OSD_SUBDEV_NAME,
0413     .id     = -1,
0414     .num_resources  = ARRAY_SIZE(dm355_osd_resources),
0415     .resource   = dm355_osd_resources,
0416     .dev        = {
0417         .dma_mask       = &vpfe_capture_dma_mask,
0418         .coherent_dma_mask  = DMA_BIT_MASK(32),
0419     },
0420 };
0421 
0422 static struct resource dm355_venc_resources[] = {
0423     {
0424         .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
0425         .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
0426         .flags  = IORESOURCE_IRQ,
0427     },
0428     /* venc registers io space */
0429     {
0430         .start  = DM355_VENC_BASE,
0431         .end    = DM355_VENC_BASE + 0x17f,
0432         .flags  = IORESOURCE_MEM,
0433     },
0434     /* VDAC config register io space */
0435     {
0436         .start  = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
0437         .end    = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
0438         .flags  = IORESOURCE_MEM,
0439     },
0440 };
0441 
0442 static struct resource dm355_v4l2_disp_resources[] = {
0443     {
0444         .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
0445         .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
0446         .flags  = IORESOURCE_IRQ,
0447     },
0448     /* venc registers io space */
0449     {
0450         .start  = DM355_VENC_BASE,
0451         .end    = DM355_VENC_BASE + 0x17f,
0452         .flags  = IORESOURCE_MEM,
0453     },
0454 };
0455 
0456 static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
0457 {
0458     switch (if_type) {
0459     case MEDIA_BUS_FMT_SGRBG8_1X8:
0460         davinci_cfg_reg(DM355_VOUT_FIELD_G70);
0461         break;
0462     case MEDIA_BUS_FMT_YUYV10_1X20:
0463         if (field)
0464             davinci_cfg_reg(DM355_VOUT_FIELD);
0465         else
0466             davinci_cfg_reg(DM355_VOUT_FIELD_G70);
0467         break;
0468     default:
0469         return -EINVAL;
0470     }
0471 
0472     davinci_cfg_reg(DM355_VOUT_COUTL_EN);
0473     davinci_cfg_reg(DM355_VOUT_COUTH_EN);
0474 
0475     return 0;
0476 }
0477 
0478 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
0479                    unsigned int pclock)
0480 {
0481     void __iomem *vpss_clk_ctrl_reg;
0482 
0483     vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
0484 
0485     switch (type) {
0486     case VPBE_ENC_STD:
0487         writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
0488                vpss_clk_ctrl_reg);
0489         break;
0490     case VPBE_ENC_DV_TIMINGS:
0491         if (pclock > 27000000)
0492             /*
0493              * For HD, use external clock source since we cannot
0494              * support HD mode with internal clocks.
0495              */
0496             writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
0497         break;
0498     default:
0499         return -EINVAL;
0500     }
0501 
0502     return 0;
0503 }
0504 
0505 static struct platform_device dm355_vpbe_display = {
0506     .name       = "vpbe-v4l2",
0507     .id     = -1,
0508     .num_resources  = ARRAY_SIZE(dm355_v4l2_disp_resources),
0509     .resource   = dm355_v4l2_disp_resources,
0510     .dev        = {
0511         .dma_mask       = &vpfe_capture_dma_mask,
0512         .coherent_dma_mask  = DMA_BIT_MASK(32),
0513     },
0514 };
0515 
0516 static struct venc_platform_data dm355_venc_pdata = {
0517     .setup_pinmux   = dm355_vpbe_setup_pinmux,
0518     .setup_clock    = dm355_venc_setup_clock,
0519 };
0520 
0521 static struct platform_device dm355_venc_dev = {
0522     .name       = DM355_VPBE_VENC_SUBDEV_NAME,
0523     .id     = -1,
0524     .num_resources  = ARRAY_SIZE(dm355_venc_resources),
0525     .resource   = dm355_venc_resources,
0526     .dev        = {
0527         .dma_mask       = &vpfe_capture_dma_mask,
0528         .coherent_dma_mask  = DMA_BIT_MASK(32),
0529         .platform_data      = (void *)&dm355_venc_pdata,
0530     },
0531 };
0532 
0533 static struct platform_device dm355_vpbe_dev = {
0534     .name       = "vpbe_controller",
0535     .id     = -1,
0536     .dev        = {
0537         .dma_mask       = &vpfe_capture_dma_mask,
0538         .coherent_dma_mask  = DMA_BIT_MASK(32),
0539     },
0540 };
0541 
0542 static struct resource dm355_gpio_resources[] = {
0543     {   /* registers */
0544         .start  = DAVINCI_GPIO_BASE,
0545         .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
0546         .flags  = IORESOURCE_MEM,
0547     },
0548     {   /* interrupt */
0549         .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
0550         .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
0551         .flags  = IORESOURCE_IRQ,
0552     },
0553     {
0554         .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
0555         .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
0556         .flags  = IORESOURCE_IRQ,
0557     },
0558     {
0559         .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
0560         .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
0561         .flags  = IORESOURCE_IRQ,
0562     },
0563     {
0564         .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
0565         .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
0566         .flags  = IORESOURCE_IRQ,
0567     },
0568     {
0569         .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
0570         .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
0571         .flags  = IORESOURCE_IRQ,
0572     },
0573     {
0574         .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
0575         .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
0576         .flags  = IORESOURCE_IRQ,
0577     },
0578     {
0579         .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
0580         .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
0581         .flags  = IORESOURCE_IRQ,
0582     },
0583 };
0584 
0585 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
0586     .no_auto_base   = true,
0587     .base       = 0,
0588     .ngpio      = 104,
0589 };
0590 
0591 int __init dm355_gpio_register(void)
0592 {
0593     return davinci_gpio_register(dm355_gpio_resources,
0594                      ARRAY_SIZE(dm355_gpio_resources),
0595                      &dm355_gpio_platform_data);
0596 }
0597 /*----------------------------------------------------------------------*/
0598 
0599 static struct map_desc dm355_io_desc[] = {
0600     {
0601         .virtual    = IO_VIRT,
0602         .pfn        = __phys_to_pfn(IO_PHYS),
0603         .length     = IO_SIZE,
0604         .type       = MT_DEVICE
0605     },
0606 };
0607 
0608 /* Contents of JTAG ID register used to identify exact cpu type */
0609 static struct davinci_id dm355_ids[] = {
0610     {
0611         .variant    = 0x0,
0612         .part_no    = 0xb73b,
0613         .manufacturer   = 0x00f,
0614         .cpu_id     = DAVINCI_CPU_ID_DM355,
0615         .name       = "dm355",
0616     },
0617 };
0618 
0619 /*
0620  * Bottom half of timer0 is used for clockevent, top half is used for
0621  * clocksource.
0622  */
0623 static const struct davinci_timer_cfg dm355_timer_cfg = {
0624     .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
0625     .irq = {
0626         DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
0627         DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
0628     },
0629 };
0630 
0631 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
0632     {
0633         .mapbase    = DAVINCI_UART0_BASE,
0634         .irq        = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
0635         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
0636                   UPF_IOREMAP,
0637         .iotype     = UPIO_MEM,
0638         .regshift   = 2,
0639     },
0640     {
0641         .flags  = 0,
0642     }
0643 };
0644 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
0645     {
0646         .mapbase    = DAVINCI_UART1_BASE,
0647         .irq        = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
0648         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
0649                   UPF_IOREMAP,
0650         .iotype     = UPIO_MEM,
0651         .regshift   = 2,
0652     },
0653     {
0654         .flags  = 0,
0655     }
0656 };
0657 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
0658     {
0659         .mapbase    = DM355_UART2_BASE,
0660         .irq        = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
0661         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
0662                   UPF_IOREMAP,
0663         .iotype     = UPIO_MEM,
0664         .regshift   = 2,
0665     },
0666     {
0667         .flags  = 0,
0668     }
0669 };
0670 
0671 struct platform_device dm355_serial_device[] = {
0672     {
0673         .name           = "serial8250",
0674         .id         = PLAT8250_DEV_PLATFORM,
0675         .dev            = {
0676             .platform_data  = dm355_serial0_platform_data,
0677         }
0678     },
0679     {
0680         .name           = "serial8250",
0681         .id         = PLAT8250_DEV_PLATFORM1,
0682         .dev            = {
0683             .platform_data  = dm355_serial1_platform_data,
0684         }
0685     },
0686     {
0687         .name           = "serial8250",
0688         .id         = PLAT8250_DEV_PLATFORM2,
0689         .dev            = {
0690             .platform_data  = dm355_serial2_platform_data,
0691         }
0692     },
0693     {
0694     }
0695 };
0696 
0697 static const struct davinci_soc_info davinci_soc_info_dm355 = {
0698     .io_desc        = dm355_io_desc,
0699     .io_desc_num        = ARRAY_SIZE(dm355_io_desc),
0700     .jtag_id_reg        = 0x01c40028,
0701     .ids            = dm355_ids,
0702     .ids_num        = ARRAY_SIZE(dm355_ids),
0703     .pinmux_base        = DAVINCI_SYSTEM_MODULE_BASE,
0704     .pinmux_pins        = dm355_pins,
0705     .pinmux_pins_num    = ARRAY_SIZE(dm355_pins),
0706     .sram_dma       = 0x00010000,
0707     .sram_len       = SZ_32K,
0708 };
0709 
0710 void __init dm355_init_asp1(u32 evt_enable)
0711 {
0712     /* we don't use ASP1 IRQs, or we'd need to mux them ... */
0713     if (evt_enable & ASP1_TX_EVT_EN)
0714         davinci_cfg_reg(DM355_EVT8_ASP1_TX);
0715 
0716     if (evt_enable & ASP1_RX_EVT_EN)
0717         davinci_cfg_reg(DM355_EVT9_ASP1_RX);
0718 
0719     platform_device_register(&dm355_asp1_device);
0720 }
0721 
0722 void __init dm355_init(void)
0723 {
0724     davinci_common_init(&davinci_soc_info_dm355);
0725     davinci_map_sysmod();
0726 }
0727 
0728 void __init dm355_init_time(void)
0729 {
0730     void __iomem *pll1, *psc;
0731     struct clk *clk;
0732     int rv;
0733 
0734     clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
0735 
0736     pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
0737     dm355_pll1_init(NULL, pll1, NULL);
0738 
0739     psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
0740     dm355_psc_init(NULL, psc);
0741 
0742     clk = clk_get(NULL, "timer0");
0743     if (WARN_ON(IS_ERR(clk))) {
0744         pr_err("Unable to get the timer clock\n");
0745         return;
0746     }
0747 
0748     rv = davinci_timer_register(clk, &dm355_timer_cfg);
0749     WARN(rv, "Unable to register the timer: %d\n", rv);
0750 }
0751 
0752 static struct resource dm355_pll2_resources[] = {
0753     {
0754         .start  = DAVINCI_PLL2_BASE,
0755         .end    = DAVINCI_PLL2_BASE + SZ_1K - 1,
0756         .flags  = IORESOURCE_MEM,
0757     },
0758 };
0759 
0760 static struct platform_device dm355_pll2_device = {
0761     .name       = "dm355-pll2",
0762     .id     = -1,
0763     .resource   = dm355_pll2_resources,
0764     .num_resources  = ARRAY_SIZE(dm355_pll2_resources),
0765 };
0766 
0767 void __init dm355_register_clocks(void)
0768 {
0769     /* PLL1 and PSC are registered in dm355_init_time() */
0770     platform_device_register(&dm355_pll2_device);
0771 }
0772 
0773 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
0774                 struct vpbe_config *vpbe_cfg)
0775 {
0776     if (vpfe_cfg || vpbe_cfg)
0777         platform_device_register(&dm355_vpss_device);
0778 
0779     if (vpfe_cfg) {
0780         vpfe_capture_dev.dev.platform_data = vpfe_cfg;
0781         platform_device_register(&dm355_ccdc_dev);
0782         platform_device_register(&vpfe_capture_dev);
0783     }
0784 
0785     if (vpbe_cfg) {
0786         dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
0787         platform_device_register(&dm355_osd_dev);
0788         platform_device_register(&dm355_venc_dev);
0789         platform_device_register(&dm355_vpbe_dev);
0790         platform_device_register(&dm355_vpbe_display);
0791     }
0792 
0793     return 0;
0794 }
0795 
0796 static const struct davinci_aintc_config dm355_aintc_config = {
0797     .reg = {
0798         .start      = DAVINCI_ARM_INTC_BASE,
0799         .end        = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
0800         .flags      = IORESOURCE_MEM,
0801     },
0802     .num_irqs       = 64,
0803     .prios          = dm355_default_priorities,
0804 };
0805 
0806 void __init dm355_init_irq(void)
0807 {
0808     davinci_aintc_init(&dm355_aintc_config);
0809 }
0810 
0811 static int __init dm355_init_devices(void)
0812 {
0813     struct platform_device *edma_pdev;
0814     int ret = 0;
0815 
0816     if (!cpu_is_davinci_dm355())
0817         return 0;
0818 
0819     davinci_cfg_reg(DM355_INT_EDMA_CC);
0820     edma_pdev = platform_device_register_full(&dm355_edma_device);
0821     if (IS_ERR(edma_pdev)) {
0822         pr_warn("%s: Failed to register eDMA\n", __func__);
0823         return PTR_ERR(edma_pdev);
0824     }
0825 
0826     ret = davinci_init_wdt();
0827     if (ret)
0828         pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
0829 
0830     return ret;
0831 }
0832 postcore_initcall(dm355_init_devices);
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