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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * DA8XX/OMAP L1XX platform device data
0004  *
0005  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
0006  * Derived from code that was:
0007  *  Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
0008  */
0009 #include <linux/ahci_platform.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/clk.h>
0012 #include <linux/clkdev.h>
0013 #include <linux/dma-map-ops.h>
0014 #include <linux/dmaengine.h>
0015 #include <linux/init.h>
0016 #include <linux/io.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/reboot.h>
0019 #include <linux/serial_8250.h>
0020 
0021 #include "common.h"
0022 #include "cputype.h"
0023 #include "da8xx.h"
0024 #include "asp.h"
0025 #include "cpuidle.h"
0026 #include "irqs.h"
0027 #include "sram.h"
0028 
0029 #define DA8XX_TPCC_BASE         0x01c00000
0030 #define DA8XX_TPTC0_BASE        0x01c08000
0031 #define DA8XX_TPTC1_BASE        0x01c08400
0032 #define DA8XX_WDOG_BASE         0x01c21000 /* DA8XX_TIMER64P1_BASE */
0033 #define DA8XX_I2C0_BASE         0x01c22000
0034 #define DA8XX_RTC_BASE          0x01c23000
0035 #define DA8XX_PRUSS_MEM_BASE        0x01c30000
0036 #define DA8XX_MMCSD0_BASE       0x01c40000
0037 #define DA8XX_SPI0_BASE         0x01c41000
0038 #define DA830_SPI1_BASE         0x01e12000
0039 #define DA8XX_LCD_CNTRL_BASE        0x01e13000
0040 #define DA850_SATA_BASE         0x01e18000
0041 #define DA850_MMCSD1_BASE       0x01e1b000
0042 #define DA8XX_EMAC_CPPI_PORT_BASE   0x01e20000
0043 #define DA8XX_EMAC_CPGMACSS_BASE    0x01e22000
0044 #define DA8XX_EMAC_CPGMAC_BASE      0x01e23000
0045 #define DA8XX_EMAC_MDIO_BASE        0x01e24000
0046 #define DA8XX_I2C1_BASE         0x01e28000
0047 #define DA850_TPCC1_BASE        0x01e30000
0048 #define DA850_TPTC2_BASE        0x01e38000
0049 #define DA850_SPI1_BASE         0x01f0e000
0050 #define DA8XX_DDR2_CTL_BASE     0xb0000000
0051 
0052 #define DA8XX_EMAC_CTRL_REG_OFFSET  0x3000
0053 #define DA8XX_EMAC_MOD_REG_OFFSET   0x2000
0054 #define DA8XX_EMAC_RAM_OFFSET       0x0000
0055 #define DA8XX_EMAC_CTRL_RAM_SIZE    SZ_8K
0056 
0057 void __iomem *da8xx_syscfg0_base;
0058 void __iomem *da8xx_syscfg1_base;
0059 
0060 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
0061     {
0062         .mapbase    = DA8XX_UART0_BASE,
0063         .irq        = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
0064         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
0065                     UPF_IOREMAP,
0066         .iotype     = UPIO_MEM,
0067         .regshift   = 2,
0068     },
0069     {
0070         .flags  = 0,
0071     }
0072 };
0073 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
0074     {
0075         .mapbase    = DA8XX_UART1_BASE,
0076         .irq        = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
0077         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
0078                     UPF_IOREMAP,
0079         .iotype     = UPIO_MEM,
0080         .regshift   = 2,
0081     },
0082     {
0083         .flags  = 0,
0084     }
0085 };
0086 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
0087     {
0088         .mapbase    = DA8XX_UART2_BASE,
0089         .irq        = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
0090         .flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
0091                     UPF_IOREMAP,
0092         .iotype     = UPIO_MEM,
0093         .regshift   = 2,
0094     },
0095     {
0096         .flags  = 0,
0097     }
0098 };
0099 
0100 struct platform_device da8xx_serial_device[] = {
0101     {
0102         .name   = "serial8250",
0103         .id = PLAT8250_DEV_PLATFORM,
0104         .dev    = {
0105             .platform_data  = da8xx_serial0_pdata,
0106         }
0107     },
0108     {
0109         .name   = "serial8250",
0110         .id = PLAT8250_DEV_PLATFORM1,
0111         .dev    = {
0112             .platform_data  = da8xx_serial1_pdata,
0113         }
0114     },
0115     {
0116         .name   = "serial8250",
0117         .id = PLAT8250_DEV_PLATFORM2,
0118         .dev    = {
0119             .platform_data  = da8xx_serial2_pdata,
0120         }
0121     },
0122     {
0123     }
0124 };
0125 
0126 static s8 da8xx_queue_priority_mapping[][2] = {
0127     /* {event queue no, Priority} */
0128     {0, 3},
0129     {1, 7},
0130     {-1, -1}
0131 };
0132 
0133 static s8 da850_queue_priority_mapping[][2] = {
0134     /* {event queue no, Priority} */
0135     {0, 3},
0136     {-1, -1}
0137 };
0138 
0139 static struct edma_soc_info da8xx_edma0_pdata = {
0140     .queue_priority_mapping = da8xx_queue_priority_mapping,
0141     .default_queue      = EVENTQ_1,
0142 };
0143 
0144 static struct edma_soc_info da850_edma1_pdata = {
0145     .queue_priority_mapping = da850_queue_priority_mapping,
0146     .default_queue      = EVENTQ_0,
0147 };
0148 
0149 static struct resource da8xx_edma0_resources[] = {
0150     {
0151         .name   = "edma3_cc",
0152         .start  = DA8XX_TPCC_BASE,
0153         .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
0154         .flags  = IORESOURCE_MEM,
0155     },
0156     {
0157         .name   = "edma3_tc0",
0158         .start  = DA8XX_TPTC0_BASE,
0159         .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
0160         .flags  = IORESOURCE_MEM,
0161     },
0162     {
0163         .name   = "edma3_tc1",
0164         .start  = DA8XX_TPTC1_BASE,
0165         .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
0166         .flags  = IORESOURCE_MEM,
0167     },
0168     {
0169         .name   = "edma3_ccint",
0170         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
0171         .flags  = IORESOURCE_IRQ,
0172     },
0173     {
0174         .name   = "edma3_ccerrint",
0175         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
0176         .flags  = IORESOURCE_IRQ,
0177     },
0178 };
0179 
0180 static struct resource da850_edma1_resources[] = {
0181     {
0182         .name   = "edma3_cc",
0183         .start  = DA850_TPCC1_BASE,
0184         .end    = DA850_TPCC1_BASE + SZ_32K - 1,
0185         .flags  = IORESOURCE_MEM,
0186     },
0187     {
0188         .name   = "edma3_tc0",
0189         .start  = DA850_TPTC2_BASE,
0190         .end    = DA850_TPTC2_BASE + SZ_1K - 1,
0191         .flags  = IORESOURCE_MEM,
0192     },
0193     {
0194         .name   = "edma3_ccint",
0195         .start  = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
0196         .flags  = IORESOURCE_IRQ,
0197     },
0198     {
0199         .name   = "edma3_ccerrint",
0200         .start  = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
0201         .flags  = IORESOURCE_IRQ,
0202     },
0203 };
0204 
0205 static const struct platform_device_info da8xx_edma0_device __initconst = {
0206     .name       = "edma",
0207     .id     = 0,
0208     .dma_mask   = DMA_BIT_MASK(32),
0209     .res        = da8xx_edma0_resources,
0210     .num_res    = ARRAY_SIZE(da8xx_edma0_resources),
0211     .data       = &da8xx_edma0_pdata,
0212     .size_data  = sizeof(da8xx_edma0_pdata),
0213 };
0214 
0215 static const struct platform_device_info da850_edma1_device __initconst = {
0216     .name       = "edma",
0217     .id     = 1,
0218     .dma_mask   = DMA_BIT_MASK(32),
0219     .res        = da850_edma1_resources,
0220     .num_res    = ARRAY_SIZE(da850_edma1_resources),
0221     .data       = &da850_edma1_pdata,
0222     .size_data  = sizeof(da850_edma1_pdata),
0223 };
0224 
0225 static const struct dma_slave_map da830_edma_map[] = {
0226     { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
0227     { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
0228     { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
0229     { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
0230     { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
0231     { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
0232     { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
0233     { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
0234     { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
0235     { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
0236     { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
0237     { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
0238 };
0239 
0240 int __init da830_register_edma(struct edma_rsv_info *rsv)
0241 {
0242     struct platform_device *edma_pdev;
0243 
0244     da8xx_edma0_pdata.rsv = rsv;
0245 
0246     da8xx_edma0_pdata.slave_map = da830_edma_map;
0247     da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
0248 
0249     edma_pdev = platform_device_register_full(&da8xx_edma0_device);
0250     return PTR_ERR_OR_ZERO(edma_pdev);
0251 }
0252 
0253 static const struct dma_slave_map da850_edma0_map[] = {
0254     { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
0255     { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
0256     { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
0257     { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
0258     { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
0259     { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
0260     { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
0261     { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
0262     { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
0263     { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
0264     { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
0265     { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
0266 };
0267 
0268 static const struct dma_slave_map da850_edma1_map[] = {
0269     { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
0270     { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
0271 };
0272 
0273 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
0274 {
0275     struct platform_device *edma_pdev;
0276 
0277     if (rsv) {
0278         da8xx_edma0_pdata.rsv = rsv[0];
0279         da850_edma1_pdata.rsv = rsv[1];
0280     }
0281 
0282     da8xx_edma0_pdata.slave_map = da850_edma0_map;
0283     da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
0284 
0285     edma_pdev = platform_device_register_full(&da8xx_edma0_device);
0286     if (IS_ERR(edma_pdev)) {
0287         pr_warn("%s: Failed to register eDMA0\n", __func__);
0288         return PTR_ERR(edma_pdev);
0289     }
0290 
0291     da850_edma1_pdata.slave_map = da850_edma1_map;
0292     da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
0293 
0294     edma_pdev = platform_device_register_full(&da850_edma1_device);
0295     return PTR_ERR_OR_ZERO(edma_pdev);
0296 }
0297 
0298 static struct resource da8xx_i2c_resources0[] = {
0299     {
0300         .start  = DA8XX_I2C0_BASE,
0301         .end    = DA8XX_I2C0_BASE + SZ_4K - 1,
0302         .flags  = IORESOURCE_MEM,
0303     },
0304     {
0305         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
0306         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
0307         .flags  = IORESOURCE_IRQ,
0308     },
0309 };
0310 
0311 static struct platform_device da8xx_i2c_device0 = {
0312     .name       = "i2c_davinci",
0313     .id     = 1,
0314     .num_resources  = ARRAY_SIZE(da8xx_i2c_resources0),
0315     .resource   = da8xx_i2c_resources0,
0316 };
0317 
0318 static struct resource da8xx_i2c_resources1[] = {
0319     {
0320         .start  = DA8XX_I2C1_BASE,
0321         .end    = DA8XX_I2C1_BASE + SZ_4K - 1,
0322         .flags  = IORESOURCE_MEM,
0323     },
0324     {
0325         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
0326         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
0327         .flags  = IORESOURCE_IRQ,
0328     },
0329 };
0330 
0331 static struct platform_device da8xx_i2c_device1 = {
0332     .name       = "i2c_davinci",
0333     .id     = 2,
0334     .num_resources  = ARRAY_SIZE(da8xx_i2c_resources1),
0335     .resource   = da8xx_i2c_resources1,
0336 };
0337 
0338 int __init da8xx_register_i2c(int instance,
0339         struct davinci_i2c_platform_data *pdata)
0340 {
0341     struct platform_device *pdev;
0342 
0343     if (instance == 0)
0344         pdev = &da8xx_i2c_device0;
0345     else if (instance == 1)
0346         pdev = &da8xx_i2c_device1;
0347     else
0348         return -EINVAL;
0349 
0350     pdev->dev.platform_data = pdata;
0351     return platform_device_register(pdev);
0352 }
0353 
0354 static struct resource da8xx_watchdog_resources[] = {
0355     {
0356         .start  = DA8XX_WDOG_BASE,
0357         .end    = DA8XX_WDOG_BASE + SZ_4K - 1,
0358         .flags  = IORESOURCE_MEM,
0359     },
0360 };
0361 
0362 static struct platform_device da8xx_wdt_device = {
0363     .name       = "davinci-wdt",
0364     .id     = -1,
0365     .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
0366     .resource   = da8xx_watchdog_resources,
0367 };
0368 
0369 int __init da8xx_register_watchdog(void)
0370 {
0371     return platform_device_register(&da8xx_wdt_device);
0372 }
0373 
0374 static struct resource da8xx_emac_resources[] = {
0375     {
0376         .start  = DA8XX_EMAC_CPPI_PORT_BASE,
0377         .end    = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
0378         .flags  = IORESOURCE_MEM,
0379     },
0380     {
0381         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
0382         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
0383         .flags  = IORESOURCE_IRQ,
0384     },
0385     {
0386         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
0387         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
0388         .flags  = IORESOURCE_IRQ,
0389     },
0390     {
0391         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
0392         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
0393         .flags  = IORESOURCE_IRQ,
0394     },
0395     {
0396         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
0397         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
0398         .flags  = IORESOURCE_IRQ,
0399     },
0400 };
0401 
0402 struct emac_platform_data da8xx_emac_pdata = {
0403     .ctrl_reg_offset    = DA8XX_EMAC_CTRL_REG_OFFSET,
0404     .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
0405     .ctrl_ram_offset    = DA8XX_EMAC_RAM_OFFSET,
0406     .ctrl_ram_size      = DA8XX_EMAC_CTRL_RAM_SIZE,
0407     .version        = EMAC_VERSION_2,
0408 };
0409 
0410 static struct platform_device da8xx_emac_device = {
0411     .name       = "davinci_emac",
0412     .id     = 1,
0413     .dev = {
0414         .platform_data  = &da8xx_emac_pdata,
0415     },
0416     .num_resources  = ARRAY_SIZE(da8xx_emac_resources),
0417     .resource   = da8xx_emac_resources,
0418 };
0419 
0420 static struct resource da8xx_mdio_resources[] = {
0421     {
0422         .start  = DA8XX_EMAC_MDIO_BASE,
0423         .end    = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
0424         .flags  = IORESOURCE_MEM,
0425     },
0426 };
0427 
0428 static struct platform_device da8xx_mdio_device = {
0429     .name       = "davinci_mdio",
0430     .id     = 0,
0431     .num_resources  = ARRAY_SIZE(da8xx_mdio_resources),
0432     .resource   = da8xx_mdio_resources,
0433 };
0434 
0435 int __init da8xx_register_emac(void)
0436 {
0437     int ret;
0438 
0439     ret = platform_device_register(&da8xx_mdio_device);
0440     if (ret < 0)
0441         return ret;
0442 
0443     return platform_device_register(&da8xx_emac_device);
0444 }
0445 
0446 static struct resource da830_mcasp1_resources[] = {
0447     {
0448         .name   = "mpu",
0449         .start  = DAVINCI_DA830_MCASP1_REG_BASE,
0450         .end    = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
0451         .flags  = IORESOURCE_MEM,
0452     },
0453     /* TX event */
0454     {
0455         .name   = "tx",
0456         .start  = DAVINCI_DA830_DMA_MCASP1_AXEVT,
0457         .end    = DAVINCI_DA830_DMA_MCASP1_AXEVT,
0458         .flags  = IORESOURCE_DMA,
0459     },
0460     /* RX event */
0461     {
0462         .name   = "rx",
0463         .start  = DAVINCI_DA830_DMA_MCASP1_AREVT,
0464         .end    = DAVINCI_DA830_DMA_MCASP1_AREVT,
0465         .flags  = IORESOURCE_DMA,
0466     },
0467     {
0468         .name   = "common",
0469         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
0470         .flags  = IORESOURCE_IRQ,
0471     },
0472 };
0473 
0474 static struct platform_device da830_mcasp1_device = {
0475     .name       = "davinci-mcasp",
0476     .id     = 1,
0477     .num_resources  = ARRAY_SIZE(da830_mcasp1_resources),
0478     .resource   = da830_mcasp1_resources,
0479 };
0480 
0481 static struct resource da830_mcasp2_resources[] = {
0482     {
0483         .name   = "mpu",
0484         .start  = DAVINCI_DA830_MCASP2_REG_BASE,
0485         .end    = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
0486         .flags  = IORESOURCE_MEM,
0487     },
0488     /* TX event */
0489     {
0490         .name   = "tx",
0491         .start  = DAVINCI_DA830_DMA_MCASP2_AXEVT,
0492         .end    = DAVINCI_DA830_DMA_MCASP2_AXEVT,
0493         .flags  = IORESOURCE_DMA,
0494     },
0495     /* RX event */
0496     {
0497         .name   = "rx",
0498         .start  = DAVINCI_DA830_DMA_MCASP2_AREVT,
0499         .end    = DAVINCI_DA830_DMA_MCASP2_AREVT,
0500         .flags  = IORESOURCE_DMA,
0501     },
0502     {
0503         .name   = "common",
0504         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
0505         .flags  = IORESOURCE_IRQ,
0506     },
0507 };
0508 
0509 static struct platform_device da830_mcasp2_device = {
0510     .name       = "davinci-mcasp",
0511     .id     = 2,
0512     .num_resources  = ARRAY_SIZE(da830_mcasp2_resources),
0513     .resource   = da830_mcasp2_resources,
0514 };
0515 
0516 static struct resource da850_mcasp_resources[] = {
0517     {
0518         .name   = "mpu",
0519         .start  = DAVINCI_DA8XX_MCASP0_REG_BASE,
0520         .end    = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
0521         .flags  = IORESOURCE_MEM,
0522     },
0523     /* TX event */
0524     {
0525         .name   = "tx",
0526         .start  = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
0527         .end    = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
0528         .flags  = IORESOURCE_DMA,
0529     },
0530     /* RX event */
0531     {
0532         .name   = "rx",
0533         .start  = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
0534         .end    = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
0535         .flags  = IORESOURCE_DMA,
0536     },
0537     {
0538         .name   = "common",
0539         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
0540         .flags  = IORESOURCE_IRQ,
0541     },
0542 };
0543 
0544 static struct platform_device da850_mcasp_device = {
0545     .name       = "davinci-mcasp",
0546     .id     = 0,
0547     .num_resources  = ARRAY_SIZE(da850_mcasp_resources),
0548     .resource   = da850_mcasp_resources,
0549 };
0550 
0551 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
0552 {
0553     struct platform_device *pdev;
0554 
0555     switch (id) {
0556     case 0:
0557         /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
0558         pdev = &da850_mcasp_device;
0559         break;
0560     case 1:
0561         /* Valid for DA830/OMAP-L137 only */
0562         if (!cpu_is_davinci_da830())
0563             return;
0564         pdev = &da830_mcasp1_device;
0565         break;
0566     case 2:
0567         /* Valid for DA830/OMAP-L137 only */
0568         if (!cpu_is_davinci_da830())
0569             return;
0570         pdev = &da830_mcasp2_device;
0571         break;
0572     default:
0573         return;
0574     }
0575 
0576     pdev->dev.platform_data = pdata;
0577     platform_device_register(pdev);
0578 }
0579 
0580 static struct resource da8xx_pruss_resources[] = {
0581     {
0582         .start  = DA8XX_PRUSS_MEM_BASE,
0583         .end    = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
0584         .flags  = IORESOURCE_MEM,
0585     },
0586     {
0587         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
0588         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
0589         .flags  = IORESOURCE_IRQ,
0590     },
0591     {
0592         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
0593         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
0594         .flags  = IORESOURCE_IRQ,
0595     },
0596     {
0597         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
0598         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
0599         .flags  = IORESOURCE_IRQ,
0600     },
0601     {
0602         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
0603         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
0604         .flags  = IORESOURCE_IRQ,
0605     },
0606     {
0607         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
0608         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
0609         .flags  = IORESOURCE_IRQ,
0610     },
0611     {
0612         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
0613         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
0614         .flags  = IORESOURCE_IRQ,
0615     },
0616     {
0617         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
0618         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
0619         .flags  = IORESOURCE_IRQ,
0620     },
0621     {
0622         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
0623         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
0624         .flags  = IORESOURCE_IRQ,
0625     },
0626 };
0627 
0628 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
0629     .pintc_base = 0x4000,
0630 };
0631 
0632 static struct platform_device da8xx_uio_pruss_dev = {
0633     .name       = "pruss_uio",
0634     .id     = -1,
0635     .num_resources  = ARRAY_SIZE(da8xx_pruss_resources),
0636     .resource   = da8xx_pruss_resources,
0637     .dev        = {
0638         .coherent_dma_mask  = DMA_BIT_MASK(32),
0639         .platform_data      = &da8xx_uio_pruss_pdata,
0640     }
0641 };
0642 
0643 int __init da8xx_register_uio_pruss(void)
0644 {
0645     da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
0646     return platform_device_register(&da8xx_uio_pruss_dev);
0647 }
0648 
0649 static struct lcd_ctrl_config lcd_cfg = {
0650     .panel_shade        = COLOR_ACTIVE,
0651     .bpp            = 16,
0652 };
0653 
0654 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
0655     .manu_name      = "sharp",
0656     .controller_data    = &lcd_cfg,
0657     .type           = "Sharp_LCD035Q3DG01",
0658 };
0659 
0660 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
0661     .manu_name      = "sharp",
0662     .controller_data    = &lcd_cfg,
0663     .type           = "Sharp_LK043T1DG01",
0664 };
0665 
0666 static struct resource da8xx_lcdc_resources[] = {
0667     [0] = { /* registers */
0668         .start  = DA8XX_LCD_CNTRL_BASE,
0669         .end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
0670         .flags  = IORESOURCE_MEM,
0671     },
0672     [1] = { /* interrupt */
0673         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
0674         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
0675         .flags  = IORESOURCE_IRQ,
0676     },
0677 };
0678 
0679 static struct platform_device da8xx_lcdc_device = {
0680     .name       = "da8xx_lcdc",
0681     .id     = 0,
0682     .num_resources  = ARRAY_SIZE(da8xx_lcdc_resources),
0683     .resource   = da8xx_lcdc_resources,
0684     .dev        = {
0685         .coherent_dma_mask  = DMA_BIT_MASK(32),
0686     }
0687 };
0688 
0689 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
0690 {
0691     da8xx_lcdc_device.dev.platform_data = pdata;
0692     return platform_device_register(&da8xx_lcdc_device);
0693 }
0694 
0695 static struct resource da8xx_gpio_resources[] = {
0696     { /* registers */
0697         .start  = DA8XX_GPIO_BASE,
0698         .end    = DA8XX_GPIO_BASE + SZ_4K - 1,
0699         .flags  = IORESOURCE_MEM,
0700     },
0701     { /* interrupt */
0702         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
0703         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
0704         .flags  = IORESOURCE_IRQ,
0705     },
0706     {
0707         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
0708         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
0709         .flags  = IORESOURCE_IRQ,
0710     },
0711     {
0712         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
0713         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
0714         .flags  = IORESOURCE_IRQ,
0715     },
0716     {
0717         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
0718         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
0719         .flags  = IORESOURCE_IRQ,
0720     },
0721     {
0722         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
0723         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
0724         .flags  = IORESOURCE_IRQ,
0725     },
0726     {
0727         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
0728         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
0729         .flags  = IORESOURCE_IRQ,
0730     },
0731     {
0732         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
0733         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
0734         .flags  = IORESOURCE_IRQ,
0735     },
0736     {
0737         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
0738         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
0739         .flags  = IORESOURCE_IRQ,
0740     },
0741     {
0742         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
0743         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
0744         .flags  = IORESOURCE_IRQ,
0745     },
0746 };
0747 
0748 static struct platform_device da8xx_gpio_device = {
0749     .name       = "davinci_gpio",
0750     .id     = -1,
0751     .num_resources  = ARRAY_SIZE(da8xx_gpio_resources),
0752     .resource   = da8xx_gpio_resources,
0753 };
0754 
0755 int __init da8xx_register_gpio(void *pdata)
0756 {
0757     da8xx_gpio_device.dev.platform_data = pdata;
0758     return platform_device_register(&da8xx_gpio_device);
0759 }
0760 
0761 static struct resource da8xx_mmcsd0_resources[] = {
0762     {       /* registers */
0763         .start  = DA8XX_MMCSD0_BASE,
0764         .end    = DA8XX_MMCSD0_BASE + SZ_4K - 1,
0765         .flags  = IORESOURCE_MEM,
0766     },
0767     {       /* interrupt */
0768         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
0769         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
0770         .flags  = IORESOURCE_IRQ,
0771     },
0772 };
0773 
0774 static struct platform_device da8xx_mmcsd0_device = {
0775     .name       = "da830-mmc",
0776     .id     = 0,
0777     .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
0778     .resource   = da8xx_mmcsd0_resources,
0779 };
0780 
0781 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
0782 {
0783     da8xx_mmcsd0_device.dev.platform_data = config;
0784     return platform_device_register(&da8xx_mmcsd0_device);
0785 }
0786 
0787 #ifdef CONFIG_ARCH_DAVINCI_DA850
0788 static struct resource da850_mmcsd1_resources[] = {
0789     {       /* registers */
0790         .start  = DA850_MMCSD1_BASE,
0791         .end    = DA850_MMCSD1_BASE + SZ_4K - 1,
0792         .flags  = IORESOURCE_MEM,
0793     },
0794     {       /* interrupt */
0795         .start  = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
0796         .end    = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
0797         .flags  = IORESOURCE_IRQ,
0798     },
0799 };
0800 
0801 static struct platform_device da850_mmcsd1_device = {
0802     .name       = "da830-mmc",
0803     .id     = 1,
0804     .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
0805     .resource   = da850_mmcsd1_resources,
0806 };
0807 
0808 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
0809 {
0810     da850_mmcsd1_device.dev.platform_data = config;
0811     return platform_device_register(&da850_mmcsd1_device);
0812 }
0813 #endif
0814 
0815 static struct resource da8xx_rproc_resources[] = {
0816     { /* DSP boot address */
0817         .name       = "host1cfg",
0818         .start      = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
0819         .end        = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
0820         .flags      = IORESOURCE_MEM,
0821     },
0822     { /* DSP interrupt registers */
0823         .name       = "chipsig",
0824         .start      = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
0825         .end        = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
0826         .flags      = IORESOURCE_MEM,
0827     },
0828     { /* DSP L2 RAM */
0829         .name       = "l2sram",
0830         .start      = DA8XX_DSP_L2_RAM_BASE,
0831         .end        = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
0832         .flags      = IORESOURCE_MEM,
0833     },
0834     { /* DSP L1P RAM */
0835         .name       = "l1pram",
0836         .start      = DA8XX_DSP_L1P_RAM_BASE,
0837         .end        = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
0838         .flags      = IORESOURCE_MEM,
0839     },
0840     { /* DSP L1D RAM */
0841         .name       = "l1dram",
0842         .start      = DA8XX_DSP_L1D_RAM_BASE,
0843         .end        = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
0844         .flags      = IORESOURCE_MEM,
0845     },
0846     { /* dsp irq */
0847         .start      = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
0848         .end        = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
0849         .flags      = IORESOURCE_IRQ,
0850     },
0851 };
0852 
0853 static struct platform_device da8xx_dsp = {
0854     .name   = "davinci-rproc",
0855     .dev    = {
0856         .coherent_dma_mask  = DMA_BIT_MASK(32),
0857     },
0858     .num_resources  = ARRAY_SIZE(da8xx_rproc_resources),
0859     .resource   = da8xx_rproc_resources,
0860 };
0861 
0862 static bool rproc_mem_inited __initdata;
0863 
0864 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
0865 
0866 static phys_addr_t rproc_base __initdata;
0867 static unsigned long rproc_size __initdata;
0868 
0869 static int __init early_rproc_mem(char *p)
0870 {
0871     char *endp;
0872 
0873     if (p == NULL)
0874         return 0;
0875 
0876     rproc_size = memparse(p, &endp);
0877     if (*endp == '@')
0878         rproc_base = memparse(endp + 1, NULL);
0879 
0880     return 0;
0881 }
0882 early_param("rproc_mem", early_rproc_mem);
0883 
0884 void __init da8xx_rproc_reserve_cma(void)
0885 {
0886     struct cma *cma;
0887     int ret;
0888 
0889     if (!rproc_base || !rproc_size) {
0890         pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
0891                "    'nn' and 'address' must both be non-zero\n",
0892                __func__);
0893 
0894         return;
0895     }
0896 
0897     pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
0898         __func__, rproc_size, (unsigned long)rproc_base);
0899 
0900     ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
0901             true);
0902     if (ret) {
0903         pr_err("%s: dma_contiguous_reserve_area failed %d\n",
0904             __func__, ret);
0905         return;
0906     }
0907     da8xx_dsp.dev.cma_area = cma;
0908     rproc_mem_inited = true;
0909 }
0910 #else
0911 
0912 void __init da8xx_rproc_reserve_cma(void)
0913 {
0914 }
0915 
0916 #endif
0917 
0918 int __init da8xx_register_rproc(void)
0919 {
0920     int ret;
0921 
0922     if (!rproc_mem_inited) {
0923         pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
0924             __func__);
0925         return -ENOMEM;
0926     }
0927 
0928     ret = platform_device_register(&da8xx_dsp);
0929     if (ret)
0930         pr_err("%s: can't register DSP device: %d\n", __func__, ret);
0931 
0932     return ret;
0933 };
0934 
0935 static struct resource da8xx_rtc_resources[] = {
0936     {
0937         .start      = DA8XX_RTC_BASE,
0938         .end        = DA8XX_RTC_BASE + SZ_4K - 1,
0939         .flags      = IORESOURCE_MEM,
0940     },
0941     { /* timer irq */
0942         .start      = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
0943         .end        = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
0944         .flags      = IORESOURCE_IRQ,
0945     },
0946     { /* alarm irq */
0947         .start      = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
0948         .end        = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
0949         .flags      = IORESOURCE_IRQ,
0950     },
0951 };
0952 
0953 static struct platform_device da8xx_rtc_device = {
0954     .name           = "da830-rtc",
0955     .id             = -1,
0956     .num_resources  = ARRAY_SIZE(da8xx_rtc_resources),
0957     .resource   = da8xx_rtc_resources,
0958 };
0959 
0960 int da8xx_register_rtc(void)
0961 {
0962     return platform_device_register(&da8xx_rtc_device);
0963 }
0964 
0965 static void __iomem *da8xx_ddr2_ctlr_base;
0966 void __iomem * __init da8xx_get_mem_ctlr(void)
0967 {
0968     if (da8xx_ddr2_ctlr_base)
0969         return da8xx_ddr2_ctlr_base;
0970 
0971     da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
0972     if (!da8xx_ddr2_ctlr_base)
0973         pr_warn("%s: Unable to map DDR2 controller", __func__);
0974 
0975     return da8xx_ddr2_ctlr_base;
0976 }
0977 
0978 static struct resource da8xx_cpuidle_resources[] = {
0979     {
0980         .start      = DA8XX_DDR2_CTL_BASE,
0981         .end        = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
0982         .flags      = IORESOURCE_MEM,
0983     },
0984 };
0985 
0986 /* DA8XX devices support DDR2 power down */
0987 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
0988     .ddr2_pdown = 1,
0989 };
0990 
0991 
0992 static struct platform_device da8xx_cpuidle_device = {
0993     .name           = "cpuidle-davinci",
0994     .num_resources      = ARRAY_SIZE(da8xx_cpuidle_resources),
0995     .resource       = da8xx_cpuidle_resources,
0996     .dev = {
0997         .platform_data  = &da8xx_cpuidle_pdata,
0998     },
0999 };
1000 
1001 int __init da8xx_register_cpuidle(void)
1002 {
1003     da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
1004 
1005     return platform_device_register(&da8xx_cpuidle_device);
1006 }
1007 
1008 static struct resource da8xx_spi0_resources[] = {
1009     [0] = {
1010         .start  = DA8XX_SPI0_BASE,
1011         .end    = DA8XX_SPI0_BASE + SZ_4K - 1,
1012         .flags  = IORESOURCE_MEM,
1013     },
1014     [1] = {
1015         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1016         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1017         .flags  = IORESOURCE_IRQ,
1018     },
1019 };
1020 
1021 static struct resource da8xx_spi1_resources[] = {
1022     [0] = {
1023         .start  = DA830_SPI1_BASE,
1024         .end    = DA830_SPI1_BASE + SZ_4K - 1,
1025         .flags  = IORESOURCE_MEM,
1026     },
1027     [1] = {
1028         .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1029         .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1030         .flags  = IORESOURCE_IRQ,
1031     },
1032 };
1033 
1034 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
1035     [0] = {
1036         .version    = SPI_VERSION_2,
1037         .intr_line  = 1,
1038         .dma_event_q    = EVENTQ_0,
1039         .prescaler_limit = 2,
1040     },
1041     [1] = {
1042         .version    = SPI_VERSION_2,
1043         .intr_line  = 1,
1044         .dma_event_q    = EVENTQ_0,
1045         .prescaler_limit = 2,
1046     },
1047 };
1048 
1049 static struct platform_device da8xx_spi_device[] = {
1050     [0] = {
1051         .name       = "spi_davinci",
1052         .id     = 0,
1053         .num_resources  = ARRAY_SIZE(da8xx_spi0_resources),
1054         .resource   = da8xx_spi0_resources,
1055         .dev        = {
1056             .platform_data = &da8xx_spi_pdata[0],
1057         },
1058     },
1059     [1] = {
1060         .name       = "spi_davinci",
1061         .id     = 1,
1062         .num_resources  = ARRAY_SIZE(da8xx_spi1_resources),
1063         .resource   = da8xx_spi1_resources,
1064         .dev        = {
1065             .platform_data = &da8xx_spi_pdata[1],
1066         },
1067     },
1068 };
1069 
1070 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1071 {
1072     if (instance < 0 || instance > 1)
1073         return -EINVAL;
1074 
1075     da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1076 
1077     if (instance == 1 && cpu_is_davinci_da850()) {
1078         da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1079         da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1080     }
1081 
1082     return platform_device_register(&da8xx_spi_device[instance]);
1083 }
1084 
1085 #ifdef CONFIG_ARCH_DAVINCI_DA850
1086 int __init da850_register_sata_refclk(int rate)
1087 {
1088     struct clk *clk;
1089 
1090     clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
1091     if (IS_ERR(clk))
1092         return PTR_ERR(clk);
1093 
1094     return clk_register_clkdev(clk, "refclk", "ahci_da850");
1095 }
1096 
1097 static struct resource da850_sata_resources[] = {
1098     {
1099         .start  = DA850_SATA_BASE,
1100         .end    = DA850_SATA_BASE + 0x1fff,
1101         .flags  = IORESOURCE_MEM,
1102     },
1103     {
1104         .start  = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1105         .end    = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1106         .flags  = IORESOURCE_MEM,
1107     },
1108     {
1109         .start  = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
1110         .flags  = IORESOURCE_IRQ,
1111     },
1112 };
1113 
1114 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1115 
1116 static struct platform_device da850_sata_device = {
1117     .name   = "ahci_da850",
1118     .id = -1,
1119     .dev    = {
1120         .dma_mask       = &da850_sata_dmamask,
1121         .coherent_dma_mask  = DMA_BIT_MASK(32),
1122     },
1123     .num_resources  = ARRAY_SIZE(da850_sata_resources),
1124     .resource   = da850_sata_resources,
1125 };
1126 
1127 int __init da850_register_sata(unsigned long refclkpn)
1128 {
1129     int ret;
1130 
1131     ret = da850_register_sata_refclk(refclkpn);
1132     if (ret)
1133         return ret;
1134 
1135     return platform_device_register(&da850_sata_device);
1136 }
1137 #endif
1138 
1139 static struct regmap *da8xx_cfgchip;
1140 
1141 static const struct regmap_config da8xx_cfgchip_config __initconst = {
1142     .name       = "cfgchip",
1143     .reg_bits   = 32,
1144     .val_bits   = 32,
1145     .reg_stride = 4,
1146     .max_register   = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
1147 };
1148 
1149 /**
1150  * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
1151  *
1152  * This is for use on non-DT boards only. For DT boards, use
1153  * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
1154  *
1155  * Returns: Pointer to the CFGCHIP regmap or negative error code.
1156  */
1157 struct regmap * __init da8xx_get_cfgchip(void)
1158 {
1159     if (IS_ERR_OR_NULL(da8xx_cfgchip))
1160         da8xx_cfgchip = regmap_init_mmio(NULL,
1161                     DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
1162                     &da8xx_cfgchip_config);
1163 
1164     return da8xx_cfgchip;
1165 }
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