arm/mach-davinci/davinci.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * This file contains the processor specific definitions
0004  * of the TI DM644x, DM355, DM365, and DM646x.
0005  *
0006  * Copyright (C) 2011 Texas Instruments Incorporated
0007  * Copyright (c) 2007 Deep Root Systems, LLC
0008  */
0009 #ifndef __DAVINCI_H
0010 #define __DAVINCI_H
0011
0012 #include <linux/clk.h>
0013 #include <linux/videodev2.h>
0014 #include <linux/davinci_emac.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/platform_data/davinci_asp.h>
0018 #include <linux/platform_data/edma.h>
0019 #include <linux/platform_data/keyscan-davinci.h>
0020
0021 #include "hardware.h"
0022
0023 #include <media/davinci/vpfe_capture.h>
0024 #include <media/davinci/vpif_types.h>
0025 #include <media/davinci/vpss.h>
0026 #include <media/davinci/vpbe_types.h>
0027 #include <media/davinci/vpbe_venc.h>
0028 #include <media/davinci/vpbe.h>
0029 #include <media/davinci/vpbe_osd.h>
0030
0031 #define DAVINCI_PLL1_BASE       0x01c40800
0032 #define DAVINCI_PLL2_BASE       0x01c40c00
0033 #define DAVINCI_PWR_SLEEP_CNTRL_BASE    0x01c41000
0034
0035 #define DAVINCI_SYSTEM_MODULE_BASE  0x01c40000
0036 #define SYSMOD_VDAC_CONFIG      0x2c
0037 #define SYSMOD_VIDCLKCTL        0x38
0038 #define SYSMOD_VPSS_CLKCTL      0x44
0039 #define SYSMOD_VDD3P3VPWDN      0x48
0040 #define SYSMOD_VSCLKDIS         0x6c
0041 #define SYSMOD_PUPDCTL1         0x7c
0042
0043 /* VPSS CLKCTL bit definitions */
0044 #define VPSS_MUXSEL_EXTCLK_ENABLE   BIT(1)
0045 #define VPSS_VENCCLKEN_ENABLE       BIT(3)
0046 #define VPSS_DACCLKEN_ENABLE        BIT(4)
0047 #define VPSS_PLLC2SYSCLK5_ENABLE    BIT(5)
0048
0049 extern void __iomem *davinci_sysmod_base;
0050 #define DAVINCI_SYSMOD_VIRT(x)  (davinci_sysmod_base + (x))
0051 void davinci_map_sysmod(void);
0052
0053 #define DAVINCI_GPIO_BASE 0x01C67000
0054 int davinci_gpio_register(struct resource *res, int size, void *pdata);
0055
0056 #define DAVINCI_TIMER0_BASE     (IO_PHYS + 0x21400)
0057 #define DAVINCI_WDOG_BASE       (IO_PHYS + 0x21C00)
0058
0059 /* DM355 base addresses */
0060 #define DM355_ASYNC_EMIF_CONTROL_BASE   0x01e10000
0061 #define DM355_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
0062
0063 #define ASP1_TX_EVT_EN  1
0064 #define ASP1_RX_EVT_EN  2
0065
0066 /* DM365 base addresses */
0067 #define DM365_ASYNC_EMIF_CONTROL_BASE   0x01d10000
0068 #define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
0069 #define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
0070
0071 /* DM644x base addresses */
0072 #define DM644X_ASYNC_EMIF_CONTROL_BASE  0x01e00000
0073 #define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
0074 #define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
0075 #define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
0076 #define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
0077
0078 /* DM646x base addresses */
0079 #define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
0080 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
0081
0082 int davinci_init_wdt(void);
0083
0084 /* DM355 function declarations */
0085 void dm355_init(void);
0086 void dm355_init_time(void);
0087 void dm355_init_irq(void);
0088 void dm355_register_clocks(void);
0089 void dm355_init_spi0(unsigned chipselect_mask,
0090         const struct spi_board_info *info, unsigned len);
0091 void dm355_init_asp1(u32 evt_enable);
0092 int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
0093 int dm355_gpio_register(void);
0094
0095 /* DM365 function declarations */
0096 void dm365_init(void);
0097 void dm365_init_irq(void);
0098 void dm365_init_time(void);
0099 void dm365_register_clocks(void);
0100 void dm365_init_asp(void);
0101 void dm365_init_vc(void);
0102 void dm365_init_ks(struct davinci_ks_platform_data *pdata);
0103 void dm365_init_rtc(void);
0104 void dm365_init_spi0(unsigned chipselect_mask,
0105             const struct spi_board_info *info, unsigned len);
0106 int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
0107 int dm365_gpio_register(void);
0108
0109 /* DM644x function declarations */
0110 void dm644x_init(void);
0111 void dm644x_init_irq(void);
0112 void dm644x_init_devices(void);
0113 void dm644x_init_time(void);
0114 void dm644x_register_clocks(void);
0115 void dm644x_init_asp(void);
0116 int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
0117 int dm644x_gpio_register(void);
0118
0119 /* DM646x function declarations */
0120 void dm646x_init(void);
0121 void dm646x_init_irq(void);
0122 void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
0123 void dm646x_register_clocks(void);
0124 void dm646x_init_mcasp0(struct snd_platform_data *pdata);
0125 void dm646x_init_mcasp1(struct snd_platform_data *pdata);
0126 int dm646x_init_edma(struct edma_rsv_info *rsv);
0127 void dm646x_video_init(void);
0128 void dm646x_setup_vpif(struct vpif_display_config *,
0129                struct vpif_capture_config *);
0130 int dm646x_gpio_register(void);
0131
0132 extern struct platform_device dm365_serial_device[];
0133 extern struct platform_device dm355_serial_device[];
0134 extern struct platform_device dm644x_serial_device[];
0135 extern struct platform_device dm646x_serial_device[];
0136 #endif /*__DAVINCI_H */