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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * TI DA850/OMAP-L138 chip specific setup
0004  *
0005  * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
0006  *
0007  * Derived from: arch/arm/mach-davinci/da830.c
0008  * Original Copyrights follow:
0009  *
0010  * 2009 (c) MontaVista Software, Inc.
0011  */
0012 
0013 #include <linux/clk-provider.h>
0014 #include <linux/clk/davinci.h>
0015 #include <linux/clkdev.h>
0016 #include <linux/cpufreq.h>
0017 #include <linux/gpio.h>
0018 #include <linux/init.h>
0019 #include <linux/io.h>
0020 #include <linux/irqchip/irq-davinci-cp-intc.h>
0021 #include <linux/mfd/da8xx-cfgchip.h>
0022 #include <linux/platform_data/clk-da8xx-cfgchip.h>
0023 #include <linux/platform_data/clk-davinci-pll.h>
0024 #include <linux/platform_data/davinci-cpufreq.h>
0025 #include <linux/platform_data/gpio-davinci.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/regmap.h>
0028 #include <linux/regulator/consumer.h>
0029 #include <clocksource/timer-davinci.h>
0030 
0031 #include <asm/mach/map.h>
0032 
0033 #include "common.h"
0034 #include "cputype.h"
0035 #include "da8xx.h"
0036 #include "pm.h"
0037 #include "irqs.h"
0038 #include "mux.h"
0039 
0040 #define DA850_PLL1_BASE     0x01e1a000
0041 #define DA850_TIMER64P2_BASE    0x01f0c000
0042 #define DA850_TIMER64P3_BASE    0x01f0d000
0043 
0044 #define DA850_REF_FREQ      24000000
0045 
0046 /*
0047  * Device specific mux setup
0048  *
0049  *      soc description mux mode    mode    mux dbg
0050  *                  reg offset  mask    mode
0051  */
0052 static const struct mux_config da850_pins[] = {
0053 #ifdef CONFIG_DAVINCI_MUX
0054     /* UART0 function */
0055     MUX_CFG(DA850, NUART0_CTS,  3,  24, 15, 2,  false)
0056     MUX_CFG(DA850, NUART0_RTS,  3,  28, 15, 2,  false)
0057     MUX_CFG(DA850, UART0_RXD,   3,  16, 15, 2,  false)
0058     MUX_CFG(DA850, UART0_TXD,   3,  20, 15, 2,  false)
0059     /* UART1 function */
0060     MUX_CFG(DA850, UART1_RXD,   4,  24, 15, 2,  false)
0061     MUX_CFG(DA850, UART1_TXD,   4,  28, 15, 2,  false)
0062     /* UART2 function */
0063     MUX_CFG(DA850, UART2_RXD,   4,  16, 15, 2,  false)
0064     MUX_CFG(DA850, UART2_TXD,   4,  20, 15, 2,  false)
0065     /* I2C1 function */
0066     MUX_CFG(DA850, I2C1_SCL,    4,  16, 15, 4,  false)
0067     MUX_CFG(DA850, I2C1_SDA,    4,  20, 15, 4,  false)
0068     /* I2C0 function */
0069     MUX_CFG(DA850, I2C0_SDA,    4,  12, 15, 2,  false)
0070     MUX_CFG(DA850, I2C0_SCL,    4,  8,  15, 2,  false)
0071     /* EMAC function */
0072     MUX_CFG(DA850, MII_TXEN,    2,  4,  15, 8,  false)
0073     MUX_CFG(DA850, MII_TXCLK,   2,  8,  15, 8,  false)
0074     MUX_CFG(DA850, MII_COL,     2,  12, 15, 8,  false)
0075     MUX_CFG(DA850, MII_TXD_3,   2,  16, 15, 8,  false)
0076     MUX_CFG(DA850, MII_TXD_2,   2,  20, 15, 8,  false)
0077     MUX_CFG(DA850, MII_TXD_1,   2,  24, 15, 8,  false)
0078     MUX_CFG(DA850, MII_TXD_0,   2,  28, 15, 8,  false)
0079     MUX_CFG(DA850, MII_RXCLK,   3,  0,  15, 8,  false)
0080     MUX_CFG(DA850, MII_RXDV,    3,  4,  15, 8,  false)
0081     MUX_CFG(DA850, MII_RXER,    3,  8,  15, 8,  false)
0082     MUX_CFG(DA850, MII_CRS,     3,  12, 15, 8,  false)
0083     MUX_CFG(DA850, MII_RXD_3,   3,  16, 15, 8,  false)
0084     MUX_CFG(DA850, MII_RXD_2,   3,  20, 15, 8,  false)
0085     MUX_CFG(DA850, MII_RXD_1,   3,  24, 15, 8,  false)
0086     MUX_CFG(DA850, MII_RXD_0,   3,  28, 15, 8,  false)
0087     MUX_CFG(DA850, MDIO_CLK,    4,  0,  15, 8,  false)
0088     MUX_CFG(DA850, MDIO_D,      4,  4,  15, 8,  false)
0089     MUX_CFG(DA850, RMII_TXD_0,  14, 12, 15, 8,  false)
0090     MUX_CFG(DA850, RMII_TXD_1,  14, 8,  15, 8,  false)
0091     MUX_CFG(DA850, RMII_TXEN,   14, 16, 15, 8,  false)
0092     MUX_CFG(DA850, RMII_CRS_DV, 15, 4,  15, 8,  false)
0093     MUX_CFG(DA850, RMII_RXD_0,  14, 24, 15, 8,  false)
0094     MUX_CFG(DA850, RMII_RXD_1,  14, 20, 15, 8,  false)
0095     MUX_CFG(DA850, RMII_RXER,   14, 28, 15, 8,  false)
0096     MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0,  15, 0,  false)
0097     /* McASP function */
0098     MUX_CFG(DA850,  ACLKR,      0,  0,  15, 1,  false)
0099     MUX_CFG(DA850,  ACLKX,      0,  4,  15, 1,  false)
0100     MUX_CFG(DA850,  AFSR,       0,  8,  15, 1,  false)
0101     MUX_CFG(DA850,  AFSX,       0,  12, 15, 1,  false)
0102     MUX_CFG(DA850,  AHCLKR,     0,  16, 15, 1,  false)
0103     MUX_CFG(DA850,  AHCLKX,     0,  20, 15, 1,  false)
0104     MUX_CFG(DA850,  AMUTE,      0,  24, 15, 1,  false)
0105     MUX_CFG(DA850,  AXR_15,     1,  0,  15, 1,  false)
0106     MUX_CFG(DA850,  AXR_14,     1,  4,  15, 1,  false)
0107     MUX_CFG(DA850,  AXR_13,     1,  8,  15, 1,  false)
0108     MUX_CFG(DA850,  AXR_12,     1,  12, 15, 1,  false)
0109     MUX_CFG(DA850,  AXR_11,     1,  16, 15, 1,  false)
0110     MUX_CFG(DA850,  AXR_10,     1,  20, 15, 1,  false)
0111     MUX_CFG(DA850,  AXR_9,      1,  24, 15, 1,  false)
0112     MUX_CFG(DA850,  AXR_8,      1,  28, 15, 1,  false)
0113     MUX_CFG(DA850,  AXR_7,      2,  0,  15, 1,  false)
0114     MUX_CFG(DA850,  AXR_6,      2,  4,  15, 1,  false)
0115     MUX_CFG(DA850,  AXR_5,      2,  8,  15, 1,  false)
0116     MUX_CFG(DA850,  AXR_4,      2,  12, 15, 1,  false)
0117     MUX_CFG(DA850,  AXR_3,      2,  16, 15, 1,  false)
0118     MUX_CFG(DA850,  AXR_2,      2,  20, 15, 1,  false)
0119     MUX_CFG(DA850,  AXR_1,      2,  24, 15, 1,  false)
0120     MUX_CFG(DA850,  AXR_0,      2,  28, 15, 1,  false)
0121     /* LCD function */
0122     MUX_CFG(DA850, LCD_D_7,     16, 8,  15, 2,  false)
0123     MUX_CFG(DA850, LCD_D_6,     16, 12, 15, 2,  false)
0124     MUX_CFG(DA850, LCD_D_5,     16, 16, 15, 2,  false)
0125     MUX_CFG(DA850, LCD_D_4,     16, 20, 15, 2,  false)
0126     MUX_CFG(DA850, LCD_D_3,     16, 24, 15, 2,  false)
0127     MUX_CFG(DA850, LCD_D_2,     16, 28, 15, 2,  false)
0128     MUX_CFG(DA850, LCD_D_1,     17, 0,  15, 2,  false)
0129     MUX_CFG(DA850, LCD_D_0,     17, 4,  15, 2,  false)
0130     MUX_CFG(DA850, LCD_D_15,    17, 8,  15, 2,  false)
0131     MUX_CFG(DA850, LCD_D_14,    17, 12, 15, 2,  false)
0132     MUX_CFG(DA850, LCD_D_13,    17, 16, 15, 2,  false)
0133     MUX_CFG(DA850, LCD_D_12,    17, 20, 15, 2,  false)
0134     MUX_CFG(DA850, LCD_D_11,    17, 24, 15, 2,  false)
0135     MUX_CFG(DA850, LCD_D_10,    17, 28, 15, 2,  false)
0136     MUX_CFG(DA850, LCD_D_9,     18, 0,  15, 2,  false)
0137     MUX_CFG(DA850, LCD_D_8,     18, 4,  15, 2,  false)
0138     MUX_CFG(DA850, LCD_PCLK,    18, 24, 15, 2,  false)
0139     MUX_CFG(DA850, LCD_HSYNC,   19, 0,  15, 2,  false)
0140     MUX_CFG(DA850, LCD_VSYNC,   19, 4,  15, 2,  false)
0141     MUX_CFG(DA850, NLCD_AC_ENB_CS,  19, 24, 15, 2,  false)
0142     /* MMC/SD0 function */
0143     MUX_CFG(DA850, MMCSD0_DAT_0,    10, 8,  15, 2,  false)
0144     MUX_CFG(DA850, MMCSD0_DAT_1,    10, 12, 15, 2,  false)
0145     MUX_CFG(DA850, MMCSD0_DAT_2,    10, 16, 15, 2,  false)
0146     MUX_CFG(DA850, MMCSD0_DAT_3,    10, 20, 15, 2,  false)
0147     MUX_CFG(DA850, MMCSD0_CLK,  10, 0,  15, 2,  false)
0148     MUX_CFG(DA850, MMCSD0_CMD,  10, 4,  15, 2,  false)
0149     /* MMC/SD1 function */
0150     MUX_CFG(DA850, MMCSD1_DAT_0,    18, 8,  15, 2,  false)
0151     MUX_CFG(DA850, MMCSD1_DAT_1,    19, 16, 15, 2,  false)
0152     MUX_CFG(DA850, MMCSD1_DAT_2,    19, 12, 15, 2,  false)
0153     MUX_CFG(DA850, MMCSD1_DAT_3,    19, 8,  15, 2,  false)
0154     MUX_CFG(DA850, MMCSD1_CLK,  18, 12, 15, 2,  false)
0155     MUX_CFG(DA850, MMCSD1_CMD,  18, 16, 15, 2,  false)
0156     /* EMIF2.5/EMIFA function */
0157     MUX_CFG(DA850, EMA_D_7,     9,  0,  15, 1,  false)
0158     MUX_CFG(DA850, EMA_D_6,     9,  4,  15, 1,  false)
0159     MUX_CFG(DA850, EMA_D_5,     9,  8,  15, 1,  false)
0160     MUX_CFG(DA850, EMA_D_4,     9,  12, 15, 1,  false)
0161     MUX_CFG(DA850, EMA_D_3,     9,  16, 15, 1,  false)
0162     MUX_CFG(DA850, EMA_D_2,     9,  20, 15, 1,  false)
0163     MUX_CFG(DA850, EMA_D_1,     9,  24, 15, 1,  false)
0164     MUX_CFG(DA850, EMA_D_0,     9,  28, 15, 1,  false)
0165     MUX_CFG(DA850, EMA_A_1,     12, 24, 15, 1,  false)
0166     MUX_CFG(DA850, EMA_A_2,     12, 20, 15, 1,  false)
0167     MUX_CFG(DA850, NEMA_CS_3,   7,  4,  15, 1,  false)
0168     MUX_CFG(DA850, NEMA_CS_4,   7,  8,  15, 1,  false)
0169     MUX_CFG(DA850, NEMA_WE,     7,  16, 15, 1,  false)
0170     MUX_CFG(DA850, NEMA_OE,     7,  20, 15, 1,  false)
0171     MUX_CFG(DA850, EMA_A_0,     12, 28, 15, 1,  false)
0172     MUX_CFG(DA850, EMA_A_3,     12, 16, 15, 1,  false)
0173     MUX_CFG(DA850, EMA_A_4,     12, 12, 15, 1,  false)
0174     MUX_CFG(DA850, EMA_A_5,     12, 8,  15, 1,  false)
0175     MUX_CFG(DA850, EMA_A_6,     12, 4,  15, 1,  false)
0176     MUX_CFG(DA850, EMA_A_7,     12, 0,  15, 1,  false)
0177     MUX_CFG(DA850, EMA_A_8,     11, 28, 15, 1,  false)
0178     MUX_CFG(DA850, EMA_A_9,     11, 24, 15, 1,  false)
0179     MUX_CFG(DA850, EMA_A_10,    11, 20, 15, 1,  false)
0180     MUX_CFG(DA850, EMA_A_11,    11, 16, 15, 1,  false)
0181     MUX_CFG(DA850, EMA_A_12,    11, 12, 15, 1,  false)
0182     MUX_CFG(DA850, EMA_A_13,    11, 8,  15, 1,  false)
0183     MUX_CFG(DA850, EMA_A_14,    11, 4,  15, 1,  false)
0184     MUX_CFG(DA850, EMA_A_15,    11, 0,  15, 1,  false)
0185     MUX_CFG(DA850, EMA_A_16,    10, 28, 15, 1,  false)
0186     MUX_CFG(DA850, EMA_A_17,    10, 24, 15, 1,  false)
0187     MUX_CFG(DA850, EMA_A_18,    10, 20, 15, 1,  false)
0188     MUX_CFG(DA850, EMA_A_19,    10, 16, 15, 1,  false)
0189     MUX_CFG(DA850, EMA_A_20,    10, 12, 15, 1,  false)
0190     MUX_CFG(DA850, EMA_A_21,    10, 8,  15, 1,  false)
0191     MUX_CFG(DA850, EMA_A_22,    10, 4,  15, 1,  false)
0192     MUX_CFG(DA850, EMA_A_23,    10, 0,  15, 1,  false)
0193     MUX_CFG(DA850, EMA_D_8,     8,  28, 15, 1,  false)
0194     MUX_CFG(DA850, EMA_D_9,     8,  24, 15, 1,  false)
0195     MUX_CFG(DA850, EMA_D_10,    8,  20, 15, 1,  false)
0196     MUX_CFG(DA850, EMA_D_11,    8,  16, 15, 1,  false)
0197     MUX_CFG(DA850, EMA_D_12,    8,  12, 15, 1,  false)
0198     MUX_CFG(DA850, EMA_D_13,    8,  8,  15, 1,  false)
0199     MUX_CFG(DA850, EMA_D_14,    8,  4,  15, 1,  false)
0200     MUX_CFG(DA850, EMA_D_15,    8,  0,  15, 1,  false)
0201     MUX_CFG(DA850, EMA_BA_1,    5,  24, 15, 1,  false)
0202     MUX_CFG(DA850, EMA_CLK,     6,  0,  15, 1,  false)
0203     MUX_CFG(DA850, EMA_WAIT_1,  6,  24, 15, 1,  false)
0204     MUX_CFG(DA850, NEMA_CS_2,   7,  0,  15, 1,  false)
0205     /* GPIO function */
0206     MUX_CFG(DA850, GPIO2_4,     6,  12, 15, 8,  false)
0207     MUX_CFG(DA850, GPIO2_6,     6,  4,  15, 8,  false)
0208     MUX_CFG(DA850, GPIO2_8,     5,  28, 15, 8,  false)
0209     MUX_CFG(DA850, GPIO2_15,    5,  0,  15, 8,  false)
0210     MUX_CFG(DA850, GPIO3_12,    7,  12, 15, 8,  false)
0211     MUX_CFG(DA850, GPIO3_13,    7,  8,  15, 8,  false)
0212     MUX_CFG(DA850, GPIO4_0,     10, 28, 15, 8,  false)
0213     MUX_CFG(DA850, GPIO4_1,     10, 24, 15, 8,  false)
0214     MUX_CFG(DA850, GPIO6_9,     13, 24, 15, 8,  false)
0215     MUX_CFG(DA850, GPIO6_10,    13, 20, 15, 8,  false)
0216     MUX_CFG(DA850, GPIO6_13,    13, 8,  15, 8,  false)
0217     MUX_CFG(DA850, RTC_ALARM,   0,  28, 15, 2,  false)
0218     /* VPIF Capture */
0219     MUX_CFG(DA850, VPIF_DIN0,   15, 4,  15, 1,  false)
0220     MUX_CFG(DA850, VPIF_DIN1,   15, 0,  15, 1,  false)
0221     MUX_CFG(DA850, VPIF_DIN2,   14, 28, 15, 1,  false)
0222     MUX_CFG(DA850, VPIF_DIN3,   14, 24, 15, 1,  false)
0223     MUX_CFG(DA850, VPIF_DIN4,   14, 20, 15, 1,  false)
0224     MUX_CFG(DA850, VPIF_DIN5,   14, 16, 15, 1,  false)
0225     MUX_CFG(DA850, VPIF_DIN6,   14, 12, 15, 1,  false)
0226     MUX_CFG(DA850, VPIF_DIN7,   14, 8,  15, 1,  false)
0227     MUX_CFG(DA850, VPIF_DIN8,   16, 4,  15, 1,  false)
0228     MUX_CFG(DA850, VPIF_DIN9,   16, 0,  15, 1,  false)
0229     MUX_CFG(DA850, VPIF_DIN10,  15, 28, 15, 1,  false)
0230     MUX_CFG(DA850, VPIF_DIN11,  15, 24, 15, 1,  false)
0231     MUX_CFG(DA850, VPIF_DIN12,  15, 20, 15, 1,  false)
0232     MUX_CFG(DA850, VPIF_DIN13,  15, 16, 15, 1,  false)
0233     MUX_CFG(DA850, VPIF_DIN14,  15, 12, 15, 1,  false)
0234     MUX_CFG(DA850, VPIF_DIN15,  15, 8,  15, 1,  false)
0235     MUX_CFG(DA850, VPIF_CLKIN0, 14, 0,  15, 1,  false)
0236     MUX_CFG(DA850, VPIF_CLKIN1, 14, 4,  15, 1,  false)
0237     MUX_CFG(DA850, VPIF_CLKIN2, 19, 8,  15, 1,  false)
0238     MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1,  false)
0239     /* VPIF Display */
0240     MUX_CFG(DA850, VPIF_DOUT0,  17, 4,  15, 1,  false)
0241     MUX_CFG(DA850, VPIF_DOUT1,  17, 0,  15, 1,  false)
0242     MUX_CFG(DA850, VPIF_DOUT2,  16, 28, 15, 1,  false)
0243     MUX_CFG(DA850, VPIF_DOUT3,  16, 24, 15, 1,  false)
0244     MUX_CFG(DA850, VPIF_DOUT4,  16, 20, 15, 1,  false)
0245     MUX_CFG(DA850, VPIF_DOUT5,  16, 16, 15, 1,  false)
0246     MUX_CFG(DA850, VPIF_DOUT6,  16, 12, 15, 1,  false)
0247     MUX_CFG(DA850, VPIF_DOUT7,  16, 8,  15, 1,  false)
0248     MUX_CFG(DA850, VPIF_DOUT8,  18, 4,  15, 1,  false)
0249     MUX_CFG(DA850, VPIF_DOUT9,  18, 0,  15, 1,  false)
0250     MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1,  false)
0251     MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1,  false)
0252     MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1,  false)
0253     MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1,  false)
0254     MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1,  false)
0255     MUX_CFG(DA850, VPIF_DOUT15, 17, 8,  15, 1,  false)
0256     MUX_CFG(DA850, VPIF_CLKO2,  19, 12, 15, 1,  false)
0257     MUX_CFG(DA850, VPIF_CLKO3,  19, 20, 15, 1,  false)
0258 #endif
0259 };
0260 
0261 const short da850_i2c0_pins[] __initconst = {
0262     DA850_I2C0_SDA, DA850_I2C0_SCL,
0263     -1
0264 };
0265 
0266 const short da850_i2c1_pins[] __initconst = {
0267     DA850_I2C1_SCL, DA850_I2C1_SDA,
0268     -1
0269 };
0270 
0271 const short da850_lcdcntl_pins[] __initconst = {
0272     DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
0273     DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
0274     DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
0275     DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
0276     DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
0277     -1
0278 };
0279 
0280 const short da850_vpif_capture_pins[] __initconst = {
0281     DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
0282     DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
0283     DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
0284     DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
0285     DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
0286     DA850_VPIF_CLKIN3,
0287     -1
0288 };
0289 
0290 const short da850_vpif_display_pins[] __initconst = {
0291     DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
0292     DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
0293     DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
0294     DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
0295     DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
0296     DA850_VPIF_CLKO3,
0297     -1
0298 };
0299 
0300 static struct map_desc da850_io_desc[] = {
0301     {
0302         .virtual    = IO_VIRT,
0303         .pfn        = __phys_to_pfn(IO_PHYS),
0304         .length     = IO_SIZE,
0305         .type       = MT_DEVICE
0306     },
0307     {
0308         .virtual    = DA8XX_CP_INTC_VIRT,
0309         .pfn        = __phys_to_pfn(DA8XX_CP_INTC_BASE),
0310         .length     = DA8XX_CP_INTC_SIZE,
0311         .type       = MT_DEVICE
0312     },
0313 };
0314 
0315 /* Contents of JTAG ID register used to identify exact cpu type */
0316 static struct davinci_id da850_ids[] = {
0317     {
0318         .variant    = 0x0,
0319         .part_no    = 0xb7d1,
0320         .manufacturer   = 0x017,    /* 0x02f >> 1 */
0321         .cpu_id     = DAVINCI_CPU_ID_DA850,
0322         .name       = "da850/omap-l138",
0323     },
0324     {
0325         .variant    = 0x1,
0326         .part_no    = 0xb7d1,
0327         .manufacturer   = 0x017,    /* 0x02f >> 1 */
0328         .cpu_id     = DAVINCI_CPU_ID_DA850,
0329         .name       = "da850/omap-l138/am18x",
0330     },
0331 };
0332 
0333 /*
0334  * Bottom half of timer 0 is used for clock_event, top half for
0335  * clocksource.
0336  */
0337 static const struct davinci_timer_cfg da850_timer_cfg = {
0338     .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
0339     .irq = {
0340         DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
0341         DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
0342     },
0343 };
0344 
0345 #ifdef CONFIG_CPU_FREQ
0346 /*
0347  * Notes:
0348  * According to the TRM, minimum PLLM results in maximum power savings.
0349  * The OPP definitions below should keep the PLLM as low as possible.
0350  *
0351  * The output of the PLLM must be between 300 to 600 MHz.
0352  */
0353 struct da850_opp {
0354     unsigned int    freq;   /* in KHz */
0355     unsigned int    prediv;
0356     unsigned int    mult;
0357     unsigned int    postdiv;
0358     unsigned int    cvdd_min; /* in uV */
0359     unsigned int    cvdd_max; /* in uV */
0360 };
0361 
0362 static const struct da850_opp da850_opp_456 = {
0363     .freq       = 456000,
0364     .prediv     = 1,
0365     .mult       = 19,
0366     .postdiv    = 1,
0367     .cvdd_min   = 1300000,
0368     .cvdd_max   = 1350000,
0369 };
0370 
0371 static const struct da850_opp da850_opp_408 = {
0372     .freq       = 408000,
0373     .prediv     = 1,
0374     .mult       = 17,
0375     .postdiv    = 1,
0376     .cvdd_min   = 1300000,
0377     .cvdd_max   = 1350000,
0378 };
0379 
0380 static const struct da850_opp da850_opp_372 = {
0381     .freq       = 372000,
0382     .prediv     = 2,
0383     .mult       = 31,
0384     .postdiv    = 1,
0385     .cvdd_min   = 1200000,
0386     .cvdd_max   = 1320000,
0387 };
0388 
0389 static const struct da850_opp da850_opp_300 = {
0390     .freq       = 300000,
0391     .prediv     = 1,
0392     .mult       = 25,
0393     .postdiv    = 2,
0394     .cvdd_min   = 1200000,
0395     .cvdd_max   = 1320000,
0396 };
0397 
0398 static const struct da850_opp da850_opp_200 = {
0399     .freq       = 200000,
0400     .prediv     = 1,
0401     .mult       = 25,
0402     .postdiv    = 3,
0403     .cvdd_min   = 1100000,
0404     .cvdd_max   = 1160000,
0405 };
0406 
0407 static const struct da850_opp da850_opp_96 = {
0408     .freq       = 96000,
0409     .prediv     = 1,
0410     .mult       = 20,
0411     .postdiv    = 5,
0412     .cvdd_min   = 1000000,
0413     .cvdd_max   = 1050000,
0414 };
0415 
0416 #define OPP(freq)       \
0417     {               \
0418         .driver_data = (unsigned int) &da850_opp_##freq,    \
0419         .frequency = freq * 1000, \
0420     }
0421 
0422 static struct cpufreq_frequency_table da850_freq_table[] = {
0423     OPP(456),
0424     OPP(408),
0425     OPP(372),
0426     OPP(300),
0427     OPP(200),
0428     OPP(96),
0429     {
0430         .driver_data        = 0,
0431         .frequency  = CPUFREQ_TABLE_END,
0432     },
0433 };
0434 
0435 #ifdef CONFIG_REGULATOR
0436 static int da850_set_voltage(unsigned int index);
0437 static int da850_regulator_init(void);
0438 #endif
0439 
0440 static struct davinci_cpufreq_config cpufreq_info = {
0441     .freq_table = da850_freq_table,
0442 #ifdef CONFIG_REGULATOR
0443     .init = da850_regulator_init,
0444     .set_voltage = da850_set_voltage,
0445 #endif
0446 };
0447 
0448 #ifdef CONFIG_REGULATOR
0449 static struct regulator *cvdd;
0450 
0451 static int da850_set_voltage(unsigned int index)
0452 {
0453     struct da850_opp *opp;
0454 
0455     if (!cvdd)
0456         return -ENODEV;
0457 
0458     opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
0459 
0460     return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
0461 }
0462 
0463 static int da850_regulator_init(void)
0464 {
0465     cvdd = regulator_get(NULL, "cvdd");
0466     if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
0467                     " voltage scaling unsupported\n")) {
0468         return PTR_ERR(cvdd);
0469     }
0470 
0471     return 0;
0472 }
0473 #endif
0474 
0475 static struct platform_device da850_cpufreq_device = {
0476     .name           = "cpufreq-davinci",
0477     .dev = {
0478         .platform_data  = &cpufreq_info,
0479     },
0480     .id = -1,
0481 };
0482 
0483 unsigned int da850_max_speed = 300000;
0484 
0485 int da850_register_cpufreq(char *async_clk)
0486 {
0487     int i;
0488 
0489     /* cpufreq driver can help keep an "async" clock constant */
0490     if (async_clk)
0491         clk_add_alias("async", da850_cpufreq_device.name,
0492                             async_clk, NULL);
0493     for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
0494         if (da850_freq_table[i].frequency <= da850_max_speed) {
0495             cpufreq_info.freq_table = &da850_freq_table[i];
0496             break;
0497         }
0498     }
0499 
0500     return platform_device_register(&da850_cpufreq_device);
0501 }
0502 #else
0503 int __init da850_register_cpufreq(char *async_clk)
0504 {
0505     return 0;
0506 }
0507 #endif
0508 
0509 /* VPIF resource, platform data */
0510 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
0511 
0512 static struct resource da850_vpif_resource[] = {
0513     {
0514         .start = DA8XX_VPIF_BASE,
0515         .end   = DA8XX_VPIF_BASE + 0xfff,
0516         .flags = IORESOURCE_MEM,
0517     }
0518 };
0519 
0520 static struct platform_device da850_vpif_dev = {
0521     .name       = "vpif",
0522     .id     = -1,
0523     .dev        = {
0524         .dma_mask       = &da850_vpif_dma_mask,
0525         .coherent_dma_mask  = DMA_BIT_MASK(32),
0526     },
0527     .resource   = da850_vpif_resource,
0528     .num_resources  = ARRAY_SIZE(da850_vpif_resource),
0529 };
0530 
0531 static struct resource da850_vpif_display_resource[] = {
0532     {
0533         .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
0534         .end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
0535         .flags = IORESOURCE_IRQ,
0536     },
0537 };
0538 
0539 static struct platform_device da850_vpif_display_dev = {
0540     .name       = "vpif_display",
0541     .id     = -1,
0542     .dev        = {
0543         .dma_mask       = &da850_vpif_dma_mask,
0544         .coherent_dma_mask  = DMA_BIT_MASK(32),
0545     },
0546     .resource       = da850_vpif_display_resource,
0547     .num_resources  = ARRAY_SIZE(da850_vpif_display_resource),
0548 };
0549 
0550 static struct resource da850_vpif_capture_resource[] = {
0551     {
0552         .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
0553         .end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
0554         .flags = IORESOURCE_IRQ,
0555     },
0556     {
0557         .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
0558         .end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
0559         .flags = IORESOURCE_IRQ,
0560     },
0561 };
0562 
0563 static struct platform_device da850_vpif_capture_dev = {
0564     .name       = "vpif_capture",
0565     .id     = -1,
0566     .dev        = {
0567         .dma_mask       = &da850_vpif_dma_mask,
0568         .coherent_dma_mask  = DMA_BIT_MASK(32),
0569     },
0570     .resource       = da850_vpif_capture_resource,
0571     .num_resources  = ARRAY_SIZE(da850_vpif_capture_resource),
0572 };
0573 
0574 int __init da850_register_vpif(void)
0575 {
0576     return platform_device_register(&da850_vpif_dev);
0577 }
0578 
0579 int __init da850_register_vpif_display(struct vpif_display_config
0580                         *display_config)
0581 {
0582     da850_vpif_display_dev.dev.platform_data = display_config;
0583     return platform_device_register(&da850_vpif_display_dev);
0584 }
0585 
0586 int __init da850_register_vpif_capture(struct vpif_capture_config
0587                             *capture_config)
0588 {
0589     da850_vpif_capture_dev.dev.platform_data = capture_config;
0590     return platform_device_register(&da850_vpif_capture_dev);
0591 }
0592 
0593 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
0594     .no_auto_base   = true,
0595     .base       = 0,
0596     .ngpio      = 144,
0597 };
0598 
0599 int __init da850_register_gpio(void)
0600 {
0601     return da8xx_register_gpio(&da850_gpio_platform_data);
0602 }
0603 
0604 static const struct davinci_soc_info davinci_soc_info_da850 = {
0605     .io_desc        = da850_io_desc,
0606     .io_desc_num        = ARRAY_SIZE(da850_io_desc),
0607     .jtag_id_reg        = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
0608     .ids            = da850_ids,
0609     .ids_num        = ARRAY_SIZE(da850_ids),
0610     .pinmux_base        = DA8XX_SYSCFG0_BASE + 0x120,
0611     .pinmux_pins        = da850_pins,
0612     .pinmux_pins_num    = ARRAY_SIZE(da850_pins),
0613     .emac_pdata     = &da8xx_emac_pdata,
0614     .sram_dma       = DA8XX_SHARED_RAM_BASE,
0615     .sram_len       = SZ_128K,
0616 };
0617 
0618 void __init da850_init(void)
0619 {
0620     davinci_common_init(&davinci_soc_info_da850);
0621 
0622     da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
0623     if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
0624         return;
0625 
0626     da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
0627     WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
0628 }
0629 
0630 static const struct davinci_cp_intc_config da850_cp_intc_config = {
0631     .reg = {
0632         .start      = DA8XX_CP_INTC_BASE,
0633         .end        = DA8XX_CP_INTC_BASE + SZ_8K - 1,
0634         .flags      = IORESOURCE_MEM,
0635     },
0636     .num_irqs       = DA850_N_CP_INTC_IRQ,
0637 };
0638 
0639 void __init da850_init_irq(void)
0640 {
0641     davinci_cp_intc_init(&da850_cp_intc_config);
0642 }
0643 
0644 void __init da850_init_time(void)
0645 {
0646     void __iomem *pll0;
0647     struct regmap *cfgchip;
0648     struct clk *clk;
0649     int rv;
0650 
0651     clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
0652 
0653     pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
0654     cfgchip = da8xx_get_cfgchip();
0655 
0656     da850_pll0_init(NULL, pll0, cfgchip);
0657 
0658     clk = clk_get(NULL, "timer0");
0659     if (WARN_ON(IS_ERR(clk))) {
0660         pr_err("Unable to get the timer clock\n");
0661         return;
0662     }
0663 
0664     rv = davinci_timer_register(clk, &da850_timer_cfg);
0665     WARN(rv, "Unable to register the timer: %d\n", rv);
0666 }
0667 
0668 static struct resource da850_pll1_resources[] = {
0669     {
0670         .start  = DA850_PLL1_BASE,
0671         .end    = DA850_PLL1_BASE + SZ_4K - 1,
0672         .flags  = IORESOURCE_MEM,
0673     },
0674 };
0675 
0676 static struct davinci_pll_platform_data da850_pll1_pdata;
0677 
0678 static struct platform_device da850_pll1_device = {
0679     .name       = "da850-pll1",
0680     .id     = -1,
0681     .resource   = da850_pll1_resources,
0682     .num_resources  = ARRAY_SIZE(da850_pll1_resources),
0683     .dev        = {
0684         .platform_data  = &da850_pll1_pdata,
0685     },
0686 };
0687 
0688 static struct resource da850_psc0_resources[] = {
0689     {
0690         .start  = DA8XX_PSC0_BASE,
0691         .end    = DA8XX_PSC0_BASE + SZ_4K - 1,
0692         .flags  = IORESOURCE_MEM,
0693     },
0694 };
0695 
0696 static struct platform_device da850_psc0_device = {
0697     .name       = "da850-psc0",
0698     .id     = -1,
0699     .resource   = da850_psc0_resources,
0700     .num_resources  = ARRAY_SIZE(da850_psc0_resources),
0701 };
0702 
0703 static struct resource da850_psc1_resources[] = {
0704     {
0705         .start  = DA8XX_PSC1_BASE,
0706         .end    = DA8XX_PSC1_BASE + SZ_4K - 1,
0707         .flags  = IORESOURCE_MEM,
0708     },
0709 };
0710 
0711 static struct platform_device da850_psc1_device = {
0712     .name       = "da850-psc1",
0713     .id     = -1,
0714     .resource   = da850_psc1_resources,
0715     .num_resources  = ARRAY_SIZE(da850_psc1_resources),
0716 };
0717 
0718 static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata;
0719 
0720 static struct platform_device da850_async1_clksrc_device = {
0721     .name       = "da850-async1-clksrc",
0722     .id     = -1,
0723     .dev        = {
0724         .platform_data  = &da850_async1_pdata,
0725     },
0726 };
0727 
0728 static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata;
0729 
0730 static struct platform_device da850_async3_clksrc_device = {
0731     .name       = "da850-async3-clksrc",
0732     .id     = -1,
0733     .dev        = {
0734         .platform_data  = &da850_async3_pdata,
0735     },
0736 };
0737 
0738 static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata;
0739 
0740 static struct platform_device da850_tbclksync_device = {
0741     .name       = "da830-tbclksync",
0742     .id     = -1,
0743     .dev        = {
0744         .platform_data  = &da850_tbclksync_pdata,
0745     },
0746 };
0747 
0748 void __init da850_register_clocks(void)
0749 {
0750     /* PLL0 is registered in da850_init_time() */
0751 
0752     da850_pll1_pdata.cfgchip = da8xx_get_cfgchip();
0753     platform_device_register(&da850_pll1_device);
0754 
0755     da850_async1_pdata.cfgchip = da8xx_get_cfgchip();
0756     platform_device_register(&da850_async1_clksrc_device);
0757 
0758     da850_async3_pdata.cfgchip = da8xx_get_cfgchip();
0759     platform_device_register(&da850_async3_clksrc_device);
0760 
0761     platform_device_register(&da850_psc0_device);
0762 
0763     platform_device_register(&da850_psc1_device);
0764 
0765     da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip();
0766     platform_device_register(&da850_tbclksync_device);
0767 }
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