arm/mach-davinci/clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * TI DaVinci clock definitions
0004  *
0005  * Copyright (C) 2006-2007 Texas Instruments.
0006  * Copyright (C) 2008-2009 Deep Root Systems, LLC
0007  */
0008
0009 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
0010 #define __ARCH_ARM_DAVINCI_CLOCK_H
0011
0012 /* PLL/Reset register offsets */
0013 #define PLLCTL          0x100
0014 #define PLLCTL_PLLEN    BIT(0)
0015 #define PLLCTL_PLLPWRDN BIT(1)
0016 #define PLLCTL_PLLRST   BIT(3)
0017 #define PLLCTL_PLLDIS   BIT(4)
0018 #define PLLCTL_PLLENSRC BIT(5)
0019 #define PLLCTL_CLKMODE  BIT(8)
0020
0021 #define PLLM        0x110
0022 #define PLLM_PLLM_MASK  0xff
0023
0024 #define PREDIV          0x114
0025 #define PLLDIV1         0x118
0026 #define PLLDIV2         0x11c
0027 #define PLLDIV3         0x120
0028 #define POSTDIV         0x128
0029 #define BPDIV           0x12c
0030 #define PLLCMD      0x138
0031 #define PLLSTAT     0x13c
0032 #define PLLALNCTL   0x140
0033 #define PLLDCHANGE  0x144
0034 #define PLLCKEN     0x148
0035 #define PLLCKSTAT   0x14c
0036 #define PLLSYSTAT   0x150
0037 #define PLLDIV4         0x160
0038 #define PLLDIV5         0x164
0039 #define PLLDIV6         0x168
0040 #define PLLDIV7         0x16c
0041 #define PLLDIV8         0x170
0042 #define PLLDIV9         0x174
0043 #define PLLDIV_EN       BIT(15)
0044 #define PLLDIV_RATIO_MASK 0x1f
0045
0046 /*
0047  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
0048  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
0049  * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
0050  * is ~25MHz. Units are micro seconds.
0051  */
0052 #define PLL_BYPASS_TIME     1
0053 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
0054 #define PLL_RESET_TIME      1
0055 /*
0056  * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
0057  * Units are micro seconds.
0058  */
0059 #define PLL_LOCK_TIME       20
0060
0061 #endif