Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Critical Link MityOMAP-L138 SoM
0004  *
0005  * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
0006  */
0007 
0008 #define pr_fmt(fmt) "MityOMAPL138: " fmt
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/console.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/property.h>
0015 #include <linux/mtd/partitions.h>
0016 #include <linux/notifier.h>
0017 #include <linux/nvmem-consumer.h>
0018 #include <linux/nvmem-provider.h>
0019 #include <linux/regulator/machine.h>
0020 #include <linux/i2c.h>
0021 #include <linux/etherdevice.h>
0022 #include <linux/spi/spi.h>
0023 #include <linux/spi/flash.h>
0024 
0025 #include <asm/io.h>
0026 #include <asm/mach-types.h>
0027 #include <asm/mach/arch.h>
0028 
0029 #include "common.h"
0030 #include "da8xx.h"
0031 #include "mux.h"
0032 
0033 #include <linux/platform_data/mtd-davinci.h>
0034 #include <linux/platform_data/mtd-davinci-aemif.h>
0035 #include <linux/platform_data/ti-aemif.h>
0036 #include <linux/platform_data/spi-davinci.h>
0037 
0038 #define MITYOMAPL138_PHY_ID     ""
0039 
0040 #define FACTORY_CONFIG_MAGIC    0x012C0138
0041 #define FACTORY_CONFIG_VERSION  0x00010001
0042 
0043 /* Data Held in On-Board I2C device */
0044 struct factory_config {
0045     u32 magic;
0046     u32 version;
0047     u8  mac[6];
0048     u32 fpga_type;
0049     u32 spare;
0050     u32 serialnumber;
0051     char    partnum[32];
0052 };
0053 
0054 static struct factory_config factory_config;
0055 
0056 #ifdef CONFIG_CPU_FREQ
0057 struct part_no_info {
0058     const char  *part_no;   /* part number string of interest */
0059     int     max_freq;   /* khz */
0060 };
0061 
0062 static struct part_no_info mityomapl138_pn_info[] = {
0063     {
0064         .part_no    = "L138-C",
0065         .max_freq   = 300000,
0066     },
0067     {
0068         .part_no    = "L138-D",
0069         .max_freq   = 375000,
0070     },
0071     {
0072         .part_no    = "L138-F",
0073         .max_freq   = 456000,
0074     },
0075     {
0076         .part_no    = "1808-C",
0077         .max_freq   = 300000,
0078     },
0079     {
0080         .part_no    = "1808-D",
0081         .max_freq   = 375000,
0082     },
0083     {
0084         .part_no    = "1808-F",
0085         .max_freq   = 456000,
0086     },
0087     {
0088         .part_no    = "1810-D",
0089         .max_freq   = 375000,
0090     },
0091 };
0092 
0093 static void mityomapl138_cpufreq_init(const char *partnum)
0094 {
0095     int i, ret;
0096 
0097     for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
0098         /*
0099          * the part number has additional characters beyond what is
0100          * stored in the table.  This information is not needed for
0101          * determining the speed grade, and would require several
0102          * more table entries.  Only check the first N characters
0103          * for a match.
0104          */
0105         if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
0106                  strlen(mityomapl138_pn_info[i].part_no))) {
0107             da850_max_speed = mityomapl138_pn_info[i].max_freq;
0108             break;
0109         }
0110     }
0111 
0112     ret = da850_register_cpufreq("pll0_sysclk3");
0113     if (ret)
0114         pr_warn("cpufreq registration failed: %d\n", ret);
0115 }
0116 #else
0117 static void mityomapl138_cpufreq_init(const char *partnum) { }
0118 #endif
0119 
0120 static int read_factory_config(struct notifier_block *nb,
0121                    unsigned long event, void *data)
0122 {
0123     int ret;
0124     const char *partnum = NULL;
0125     struct nvmem_device *nvmem = data;
0126 
0127     if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
0128         return NOTIFY_DONE;
0129 
0130     if (!IS_BUILTIN(CONFIG_NVMEM)) {
0131         pr_warn("Factory Config not available without CONFIG_NVMEM\n");
0132         goto bad_config;
0133     }
0134 
0135     ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
0136                 &factory_config);
0137     if (ret != sizeof(struct factory_config)) {
0138         pr_warn("Read Factory Config Failed: %d\n", ret);
0139         goto bad_config;
0140     }
0141 
0142     if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
0143         pr_warn("Factory Config Magic Wrong (%X)\n",
0144             factory_config.magic);
0145         goto bad_config;
0146     }
0147 
0148     if (factory_config.version != FACTORY_CONFIG_VERSION) {
0149         pr_warn("Factory Config Version Wrong (%X)\n",
0150             factory_config.version);
0151         goto bad_config;
0152     }
0153 
0154     partnum = factory_config.partnum;
0155     pr_info("Part Number = %s\n", partnum);
0156 
0157 bad_config:
0158     /* default maximum speed is valid for all platforms */
0159     mityomapl138_cpufreq_init(partnum);
0160 
0161     return NOTIFY_STOP;
0162 }
0163 
0164 static struct notifier_block mityomapl138_nvmem_notifier = {
0165     .notifier_call = read_factory_config,
0166 };
0167 
0168 /*
0169  * We don't define a cell for factory config as it will be accessed from the
0170  * board file using the nvmem notifier chain.
0171  */
0172 static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
0173     {
0174         .name       = "macaddr",
0175         .offset     = 0x64,
0176         .bytes      = ETH_ALEN,
0177     }
0178 };
0179 
0180 static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
0181     .nvmem_name = "1-00500",
0182     .cells      = mityomapl138_nvmem_cells,
0183     .ncells     = ARRAY_SIZE(mityomapl138_nvmem_cells),
0184 };
0185 
0186 static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
0187     .nvmem_name = "1-00500",
0188     .cell_name  = "macaddr",
0189     .dev_id     = "davinci_emac.1",
0190     .con_id     = "mac-address",
0191 };
0192 
0193 static const struct property_entry mityomapl138_fd_chip_properties[] = {
0194     PROPERTY_ENTRY_U32("pagesize", 8),
0195     PROPERTY_ENTRY_BOOL("read-only"),
0196     { }
0197 };
0198 
0199 static const struct software_node mityomapl138_fd_chip_node = {
0200     .properties = mityomapl138_fd_chip_properties,
0201 };
0202 
0203 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
0204     .bus_freq   = 100,  /* kHz */
0205     .bus_delay  = 0,    /* usec */
0206 };
0207 
0208 /* TPS65023 voltage regulator support */
0209 /* 1.2V Core */
0210 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
0211     {
0212         .supply = "cvdd",
0213     },
0214 };
0215 
0216 /* 1.8V */
0217 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
0218     {
0219         .supply = "usb0_vdda18",
0220     },
0221     {
0222         .supply = "usb1_vdda18",
0223     },
0224     {
0225         .supply = "ddr_dvdd18",
0226     },
0227     {
0228         .supply = "sata_vddr",
0229     },
0230 };
0231 
0232 /* 1.2V */
0233 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
0234     {
0235         .supply = "sata_vdd",
0236     },
0237     {
0238         .supply = "usb_cvdd",
0239     },
0240     {
0241         .supply = "pll0_vdda",
0242     },
0243     {
0244         .supply = "pll1_vdda",
0245     },
0246 };
0247 
0248 /* 1.8V Aux LDO, not used */
0249 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
0250     {
0251         .supply = "1.8v_aux",
0252     },
0253 };
0254 
0255 /* FPGA VCC Aux (2.5 or 3.3) LDO */
0256 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
0257     {
0258         .supply = "vccaux",
0259     },
0260 };
0261 
0262 static struct regulator_init_data tps65023_regulator_data[] = {
0263     /* dcdc1 */
0264     {
0265         .constraints = {
0266             .min_uV = 1150000,
0267             .max_uV = 1350000,
0268             .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
0269                       REGULATOR_CHANGE_STATUS,
0270             .boot_on = 1,
0271         },
0272         .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
0273         .consumer_supplies = tps65023_dcdc1_consumers,
0274     },
0275     /* dcdc2 */
0276     {
0277         .constraints = {
0278             .min_uV = 1800000,
0279             .max_uV = 1800000,
0280             .valid_ops_mask = REGULATOR_CHANGE_STATUS,
0281             .boot_on = 1,
0282         },
0283         .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
0284         .consumer_supplies = tps65023_dcdc2_consumers,
0285     },
0286     /* dcdc3 */
0287     {
0288         .constraints = {
0289             .min_uV = 1200000,
0290             .max_uV = 1200000,
0291             .valid_ops_mask = REGULATOR_CHANGE_STATUS,
0292             .boot_on = 1,
0293         },
0294         .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
0295         .consumer_supplies = tps65023_dcdc3_consumers,
0296     },
0297     /* ldo1 */
0298     {
0299         .constraints = {
0300             .min_uV = 1800000,
0301             .max_uV = 1800000,
0302             .valid_ops_mask = REGULATOR_CHANGE_STATUS,
0303             .boot_on = 1,
0304         },
0305         .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
0306         .consumer_supplies = tps65023_ldo1_consumers,
0307     },
0308     /* ldo2 */
0309     {
0310         .constraints = {
0311             .min_uV = 2500000,
0312             .max_uV = 3300000,
0313             .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
0314                       REGULATOR_CHANGE_STATUS,
0315             .boot_on = 1,
0316         },
0317         .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
0318         .consumer_supplies = tps65023_ldo2_consumers,
0319     },
0320 };
0321 
0322 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
0323     {
0324         I2C_BOARD_INFO("tps65023", 0x48),
0325         .platform_data = &tps65023_regulator_data[0],
0326     },
0327     {
0328         I2C_BOARD_INFO("24c02", 0x50),
0329         .swnode = &mityomapl138_fd_chip_node,
0330     },
0331 };
0332 
0333 static int __init pmic_tps65023_init(void)
0334 {
0335     return i2c_register_board_info(1, mityomap_tps65023_info,
0336                     ARRAY_SIZE(mityomap_tps65023_info));
0337 }
0338 
0339 /*
0340  * SPI Devices:
0341  *  SPI1_CS0: 8M Flash ST-M25P64-VME6G
0342  */
0343 static struct mtd_partition spi_flash_partitions[] = {
0344     [0] = {
0345         .name       = "ubl",
0346         .offset     = 0,
0347         .size       = SZ_64K,
0348         .mask_flags = MTD_WRITEABLE,
0349     },
0350     [1] = {
0351         .name       = "u-boot",
0352         .offset     = MTDPART_OFS_APPEND,
0353         .size       = SZ_512K,
0354         .mask_flags = MTD_WRITEABLE,
0355     },
0356     [2] = {
0357         .name       = "u-boot-env",
0358         .offset     = MTDPART_OFS_APPEND,
0359         .size       = SZ_64K,
0360         .mask_flags = MTD_WRITEABLE,
0361     },
0362     [3] = {
0363         .name       = "periph-config",
0364         .offset     = MTDPART_OFS_APPEND,
0365         .size       = SZ_64K,
0366         .mask_flags = MTD_WRITEABLE,
0367     },
0368     [4] = {
0369         .name       = "reserved",
0370         .offset     = MTDPART_OFS_APPEND,
0371         .size       = SZ_256K + SZ_64K,
0372     },
0373     [5] = {
0374         .name       = "kernel",
0375         .offset     = MTDPART_OFS_APPEND,
0376         .size       = SZ_2M + SZ_1M,
0377     },
0378     [6] = {
0379         .name       = "fpga",
0380         .offset     = MTDPART_OFS_APPEND,
0381         .size       = SZ_2M,
0382     },
0383     [7] = {
0384         .name       = "spare",
0385         .offset     = MTDPART_OFS_APPEND,
0386         .size       = MTDPART_SIZ_FULL,
0387     },
0388 };
0389 
0390 static struct flash_platform_data mityomapl138_spi_flash_data = {
0391     .name       = "m25p80",
0392     .parts      = spi_flash_partitions,
0393     .nr_parts   = ARRAY_SIZE(spi_flash_partitions),
0394     .type       = "m24p64",
0395 };
0396 
0397 static struct davinci_spi_config spi_eprom_config = {
0398     .io_type    = SPI_IO_TYPE_DMA,
0399     .c2tdelay   = 8,
0400     .t2cdelay   = 8,
0401 };
0402 
0403 static struct spi_board_info mityomapl138_spi_flash_info[] = {
0404     {
0405         .modalias       = "m25p80",
0406         .platform_data      = &mityomapl138_spi_flash_data,
0407         .controller_data    = &spi_eprom_config,
0408         .mode           = SPI_MODE_0,
0409         .max_speed_hz       = 30000000,
0410         .bus_num        = 1,
0411         .chip_select        = 0,
0412     },
0413 };
0414 
0415 /*
0416  * MityDSP-L138 includes a 256 MByte large-page NAND flash
0417  * (128K blocks).
0418  */
0419 static struct mtd_partition mityomapl138_nandflash_partition[] = {
0420     {
0421         .name       = "rootfs",
0422         .offset     = 0,
0423         .size       = SZ_128M,
0424         .mask_flags = 0, /* MTD_WRITEABLE, */
0425     },
0426     {
0427         .name       = "homefs",
0428         .offset     = MTDPART_OFS_APPEND,
0429         .size       = MTDPART_SIZ_FULL,
0430         .mask_flags = 0,
0431     },
0432 };
0433 
0434 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
0435     .core_chipsel   = 1,
0436     .parts      = mityomapl138_nandflash_partition,
0437     .nr_parts   = ARRAY_SIZE(mityomapl138_nandflash_partition),
0438     .engine_type    = NAND_ECC_ENGINE_TYPE_ON_HOST,
0439     .bbt_options    = NAND_BBT_USE_FLASH,
0440     .options    = NAND_BUSWIDTH_16,
0441     .ecc_bits   = 1, /* 4 bit mode is not supported with 16 bit NAND */
0442 };
0443 
0444 static struct resource mityomapl138_nandflash_resource[] = {
0445     {
0446         .start  = DA8XX_AEMIF_CS3_BASE,
0447         .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
0448         .flags  = IORESOURCE_MEM,
0449     },
0450     {
0451         .start  = DA8XX_AEMIF_CTL_BASE,
0452         .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
0453         .flags  = IORESOURCE_MEM,
0454     },
0455 };
0456 
0457 static struct platform_device mityomapl138_aemif_devices[] = {
0458     {
0459         .name       = "davinci_nand",
0460         .id     = 1,
0461         .dev        = {
0462             .platform_data  = &mityomapl138_nandflash_data,
0463         },
0464         .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
0465         .resource   = mityomapl138_nandflash_resource,
0466     },
0467 };
0468 
0469 static struct resource mityomapl138_aemif_resources[] = {
0470     {
0471         .start  = DA8XX_AEMIF_CTL_BASE,
0472         .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
0473         .flags  = IORESOURCE_MEM,
0474     },
0475 };
0476 
0477 static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
0478     {
0479         .cs = 1,
0480     },
0481 };
0482 
0483 static struct aemif_platform_data mityomapl138_aemif_pdata = {
0484     .abus_data      = mityomapl138_aemif_abus_data,
0485     .num_abus_data      = ARRAY_SIZE(mityomapl138_aemif_abus_data),
0486     .sub_devices        = mityomapl138_aemif_devices,
0487     .num_sub_devices    = ARRAY_SIZE(mityomapl138_aemif_devices),
0488 };
0489 
0490 static struct platform_device mityomapl138_aemif_device = {
0491     .name       = "ti-aemif",
0492     .id     = -1,
0493     .dev = {
0494         .platform_data  = &mityomapl138_aemif_pdata,
0495     },
0496     .resource   = mityomapl138_aemif_resources,
0497     .num_resources  = ARRAY_SIZE(mityomapl138_aemif_resources),
0498 };
0499 
0500 static void __init mityomapl138_setup_nand(void)
0501 {
0502     if (platform_device_register(&mityomapl138_aemif_device))
0503         pr_warn("%s: Cannot register AEMIF device\n", __func__);
0504 }
0505 
0506 static const short mityomap_mii_pins[] = {
0507     DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
0508     DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
0509     DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
0510     DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
0511     DA850_MDIO_D,
0512     -1
0513 };
0514 
0515 static const short mityomap_rmii_pins[] = {
0516     DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
0517     DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
0518     DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
0519     DA850_MDIO_D,
0520     -1
0521 };
0522 
0523 static void __init mityomapl138_config_emac(void)
0524 {
0525     void __iomem *cfg_chip3_base;
0526     int ret;
0527     u32 val;
0528     struct davinci_soc_info *soc_info = &davinci_soc_info;
0529 
0530     soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
0531 
0532     cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
0533     val = __raw_readl(cfg_chip3_base);
0534 
0535     if (soc_info->emac_pdata->rmii_en) {
0536         val |= BIT(8);
0537         ret = davinci_cfg_reg_list(mityomap_rmii_pins);
0538         pr_info("RMII PHY configured\n");
0539     } else {
0540         val &= ~BIT(8);
0541         ret = davinci_cfg_reg_list(mityomap_mii_pins);
0542         pr_info("MII PHY configured\n");
0543     }
0544 
0545     if (ret) {
0546         pr_warn("mii/rmii mux setup failed: %d\n", ret);
0547         return;
0548     }
0549 
0550     /* configure the CFGCHIP3 register for RMII or MII */
0551     __raw_writel(val, cfg_chip3_base);
0552 
0553     soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
0554 
0555     ret = da8xx_register_emac();
0556     if (ret)
0557         pr_warn("emac registration failed: %d\n", ret);
0558 }
0559 
0560 static void __init mityomapl138_init(void)
0561 {
0562     int ret;
0563 
0564     da850_register_clocks();
0565 
0566     /* for now, no special EDMA channels are reserved */
0567     ret = da850_register_edma(NULL);
0568     if (ret)
0569         pr_warn("edma registration failed: %d\n", ret);
0570 
0571     ret = da8xx_register_watchdog();
0572     if (ret)
0573         pr_warn("watchdog registration failed: %d\n", ret);
0574 
0575     davinci_serial_init(da8xx_serial_device);
0576 
0577     nvmem_register_notifier(&mityomapl138_nvmem_notifier);
0578     nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
0579     nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
0580 
0581     ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
0582     if (ret)
0583         pr_warn("i2c0 registration failed: %d\n", ret);
0584 
0585     ret = pmic_tps65023_init();
0586     if (ret)
0587         pr_warn("TPS65023 PMIC init failed: %d\n", ret);
0588 
0589     mityomapl138_setup_nand();
0590 
0591     ret = spi_register_board_info(mityomapl138_spi_flash_info,
0592                       ARRAY_SIZE(mityomapl138_spi_flash_info));
0593     if (ret)
0594         pr_warn("spi info registration failed: %d\n", ret);
0595 
0596     ret = da8xx_register_spi_bus(1,
0597                      ARRAY_SIZE(mityomapl138_spi_flash_info));
0598     if (ret)
0599         pr_warn("spi 1 registration failed: %d\n", ret);
0600 
0601     mityomapl138_config_emac();
0602 
0603     ret = da8xx_register_rtc();
0604     if (ret)
0605         pr_warn("rtc setup failed: %d\n", ret);
0606 
0607     ret = da8xx_register_cpuidle();
0608     if (ret)
0609         pr_warn("cpuidle registration failed: %d\n", ret);
0610 
0611     davinci_pm_init();
0612 }
0613 
0614 #ifdef CONFIG_SERIAL_8250_CONSOLE
0615 static int __init mityomapl138_console_init(void)
0616 {
0617     if (!machine_is_mityomapl138())
0618         return 0;
0619 
0620     return add_preferred_console("ttyS", 1, "115200");
0621 }
0622 console_initcall(mityomapl138_console_init);
0623 #endif
0624 
0625 static void __init mityomapl138_map_io(void)
0626 {
0627     da850_init();
0628 }
0629 
0630 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
0631     .atag_offset    = 0x100,
0632     .map_io     = mityomapl138_map_io,
0633     .init_irq   = da850_init_irq,
0634     .init_time  = da850_init_time,
0635     .init_machine   = mityomapl138_init,
0636     .init_late  = davinci_init_late,
0637     .dma_zone_size  = SZ_128M,
0638 MACHINE_END
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!