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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * TI DaVinci DM365 EVM board support
0004  *
0005  * Copyright (C) 2009 Texas Instruments Incorporated
0006  */
0007 #include <linux/kernel.h>
0008 #include <linux/init.h>
0009 #include <linux/err.h>
0010 #include <linux/i2c.h>
0011 #include <linux/io.h>
0012 #include <linux/clk.h>
0013 #include <linux/property.h>
0014 #include <linux/leds.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/mtd/partitions.h>
0017 #include <linux/slab.h>
0018 #include <linux/mtd/rawnand.h>
0019 #include <linux/nvmem-provider.h>
0020 #include <linux/input.h>
0021 #include <linux/spi/spi.h>
0022 #include <linux/spi/eeprom.h>
0023 #include <linux/v4l2-dv-timings.h>
0024 #include <linux/platform_data/ti-aemif.h>
0025 #include <linux/regulator/fixed.h>
0026 #include <linux/regulator/machine.h>
0027 
0028 #include <asm/mach-types.h>
0029 #include <asm/mach/arch.h>
0030 
0031 #include <linux/platform_data/i2c-davinci.h>
0032 #include <linux/platform_data/mmc-davinci.h>
0033 #include <linux/platform_data/mtd-davinci.h>
0034 #include <linux/platform_data/keyscan-davinci.h>
0035 
0036 #include <media/i2c/ths7303.h>
0037 #include <media/i2c/tvp514x.h>
0038 
0039 #include "mux.h"
0040 #include "common.h"
0041 #include "serial.h"
0042 #include "davinci.h"
0043 
0044 static inline int have_imager(void)
0045 {
0046     /* REVISIT when it's supported, trigger via Kconfig */
0047     return 0;
0048 }
0049 
0050 static inline int have_tvp7002(void)
0051 {
0052     /* REVISIT when it's supported, trigger via Kconfig */
0053     return 0;
0054 }
0055 
0056 #define DM365_EVM_PHY_ID        "davinci_mdio-0:01"
0057 /*
0058  * A MAX-II CPLD is used for various board control functions.
0059  */
0060 #define CPLD_OFFSET(a13a8,a2a1)     (((a13a8) << 10) + ((a2a1) << 3))
0061 
0062 #define CPLD_VERSION    CPLD_OFFSET(0,0)    /* r/o */
0063 #define CPLD_TEST   CPLD_OFFSET(0,1)
0064 #define CPLD_LEDS   CPLD_OFFSET(0,2)
0065 #define CPLD_MUX    CPLD_OFFSET(0,3)
0066 #define CPLD_SWITCH CPLD_OFFSET(1,0)    /* r/o */
0067 #define CPLD_POWER  CPLD_OFFSET(1,1)
0068 #define CPLD_VIDEO  CPLD_OFFSET(1,2)
0069 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)    /* r/o */
0070 
0071 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
0072 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)    /* r/o */
0073 
0074 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
0075 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
0076 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
0077 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
0078 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
0079 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
0080 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
0081 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
0082 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
0083 
0084 #define CPLD_RESETS CPLD_OFFSET(4,3)
0085 
0086 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
0087 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
0088 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
0089 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
0090 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
0091 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
0092 
0093 static void __iomem *cpld;
0094 
0095 
0096 /* NOTE:  this is geared for the standard config, with a socketed
0097  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
0098  * swap chips with a different block size, partitioning will
0099  * need to be changed. This NAND chip MT29F16G08FAA is the default
0100  * NAND shipped with the Spectrum Digital DM365 EVM
0101  */
0102 #define NAND_BLOCK_SIZE     SZ_128K
0103 
0104 static struct mtd_partition davinci_nand_partitions[] = {
0105     {
0106         /* UBL (a few copies) plus U-Boot */
0107         .name       = "bootloader",
0108         .offset     = 0,
0109         .size       = 30 * NAND_BLOCK_SIZE,
0110         .mask_flags = MTD_WRITEABLE, /* force read-only */
0111     }, {
0112         /* U-Boot environment */
0113         .name       = "params",
0114         .offset     = MTDPART_OFS_APPEND,
0115         .size       = 2 * NAND_BLOCK_SIZE,
0116         .mask_flags = 0,
0117     }, {
0118         .name       = "kernel",
0119         .offset     = MTDPART_OFS_APPEND,
0120         .size       = SZ_4M,
0121         .mask_flags = 0,
0122     }, {
0123         .name       = "filesystem1",
0124         .offset     = MTDPART_OFS_APPEND,
0125         .size       = SZ_512M,
0126         .mask_flags = 0,
0127     }, {
0128         .name       = "filesystem2",
0129         .offset     = MTDPART_OFS_APPEND,
0130         .size       = MTDPART_SIZ_FULL,
0131         .mask_flags = 0,
0132     }
0133     /* two blocks with bad block table (and mirror) at the end */
0134 };
0135 
0136 static struct davinci_nand_pdata davinci_nand_data = {
0137     .core_chipsel       = 0,
0138     .mask_chipsel       = BIT(14),
0139     .parts          = davinci_nand_partitions,
0140     .nr_parts       = ARRAY_SIZE(davinci_nand_partitions),
0141     .engine_type        = NAND_ECC_ENGINE_TYPE_ON_HOST,
0142     .bbt_options        = NAND_BBT_USE_FLASH,
0143     .ecc_bits       = 4,
0144 };
0145 
0146 static struct resource davinci_nand_resources[] = {
0147     {
0148         .start      = DM365_ASYNC_EMIF_DATA_CE0_BASE,
0149         .end        = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
0150         .flags      = IORESOURCE_MEM,
0151     }, {
0152         .start      = DM365_ASYNC_EMIF_CONTROL_BASE,
0153         .end        = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
0154         .flags      = IORESOURCE_MEM,
0155     },
0156 };
0157 
0158 static struct platform_device davinci_aemif_devices[] = {
0159     {
0160         .name       = "davinci_nand",
0161         .id     = 0,
0162         .num_resources  = ARRAY_SIZE(davinci_nand_resources),
0163         .resource   = davinci_nand_resources,
0164         .dev        = {
0165             .platform_data  = &davinci_nand_data,
0166         },
0167     }
0168 };
0169 
0170 static struct resource davinci_aemif_resources[] = {
0171     {
0172         .start      = DM365_ASYNC_EMIF_CONTROL_BASE,
0173         .end        = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
0174         .flags      = IORESOURCE_MEM,
0175     },
0176 };
0177 
0178 static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
0179     {
0180         .cs     = 1,
0181     },
0182 };
0183 
0184 static struct aemif_platform_data davinci_aemif_pdata = {
0185     .abus_data      = da850_evm_aemif_abus_data,
0186     .num_abus_data      = ARRAY_SIZE(da850_evm_aemif_abus_data),
0187     .sub_devices        = davinci_aemif_devices,
0188     .num_sub_devices    = ARRAY_SIZE(davinci_aemif_devices),
0189 };
0190 
0191 static struct platform_device davinci_aemif_device = {
0192     .name           = "ti-aemif",
0193     .id         = -1,
0194     .dev = {
0195         .platform_data  = &davinci_aemif_pdata,
0196     },
0197     .resource       = davinci_aemif_resources,
0198     .num_resources      = ARRAY_SIZE(davinci_aemif_resources),
0199 };
0200 
0201 static struct nvmem_cell_info davinci_nvmem_cells[] = {
0202     {
0203         .name       = "macaddr",
0204         .offset     = 0x7f00,
0205         .bytes      = ETH_ALEN,
0206     }
0207 };
0208 
0209 static struct nvmem_cell_table davinci_nvmem_cell_table = {
0210     .nvmem_name = "1-00500",
0211     .cells      = davinci_nvmem_cells,
0212     .ncells     = ARRAY_SIZE(davinci_nvmem_cells),
0213 };
0214 
0215 static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
0216     .nvmem_name = "1-00500",
0217     .cell_name  = "macaddr",
0218     .dev_id     = "davinci_emac.1",
0219     .con_id     = "mac-address",
0220 };
0221 
0222 static const struct property_entry eeprom_properties[] = {
0223     PROPERTY_ENTRY_U32("pagesize", 64),
0224     { }
0225 };
0226 
0227 static const struct software_node eeprom_node = {
0228     .properties = eeprom_properties,
0229 };
0230 
0231 static struct i2c_board_info i2c_info[] = {
0232     {
0233         I2C_BOARD_INFO("24c256", 0x50),
0234         .swnode = &eeprom_node,
0235     },
0236     {
0237         I2C_BOARD_INFO("tlv320aic3x", 0x18),
0238     },
0239 };
0240 
0241 static struct davinci_i2c_platform_data i2c_pdata = {
0242     .bus_freq   = 400   /* kHz */,
0243     .bus_delay  = 0 /* usec */,
0244 };
0245 
0246 /* Fixed regulator support */
0247 static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
0248     /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
0249     REGULATOR_SUPPLY("AVDD", "1-0018"),
0250     REGULATOR_SUPPLY("DRVDD", "1-0018"),
0251     REGULATOR_SUPPLY("IOVDD", "1-0018"),
0252 };
0253 
0254 static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
0255     /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
0256     REGULATOR_SUPPLY("DVDD", "1-0018"),
0257 };
0258 
0259 static int dm365evm_keyscan_enable(struct device *dev)
0260 {
0261     return davinci_cfg_reg(DM365_KEYSCAN);
0262 }
0263 
0264 static unsigned short dm365evm_keymap[] = {
0265     KEY_KP2,
0266     KEY_LEFT,
0267     KEY_EXIT,
0268     KEY_DOWN,
0269     KEY_ENTER,
0270     KEY_UP,
0271     KEY_KP1,
0272     KEY_RIGHT,
0273     KEY_MENU,
0274     KEY_RECORD,
0275     KEY_REWIND,
0276     KEY_KPMINUS,
0277     KEY_STOP,
0278     KEY_FASTFORWARD,
0279     KEY_KPPLUS,
0280     KEY_PLAYPAUSE,
0281     0
0282 };
0283 
0284 static struct davinci_ks_platform_data dm365evm_ks_data = {
0285     .device_enable  = dm365evm_keyscan_enable,
0286     .keymap     = dm365evm_keymap,
0287     .keymapsize = ARRAY_SIZE(dm365evm_keymap),
0288     .rep        = 1,
0289     /* Scan period = strobe + interval */
0290     .strobe     = 0x5,
0291     .interval   = 0x2,
0292     .matrix_type    = DAVINCI_KEYSCAN_MATRIX_4X4,
0293 };
0294 
0295 static int cpld_mmc_get_cd(int module)
0296 {
0297     if (!cpld)
0298         return -ENXIO;
0299 
0300     /* low == card present */
0301     return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
0302 }
0303 
0304 static int cpld_mmc_get_ro(int module)
0305 {
0306     if (!cpld)
0307         return -ENXIO;
0308 
0309     /* high == card's write protect switch active */
0310     return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
0311 }
0312 
0313 static struct davinci_mmc_config dm365evm_mmc_config = {
0314     .get_cd     = cpld_mmc_get_cd,
0315     .get_ro     = cpld_mmc_get_ro,
0316     .wires      = 4,
0317     .max_freq   = 50000000,
0318     .caps       = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
0319 };
0320 
0321 static void dm365evm_emac_configure(void)
0322 {
0323     /*
0324      * EMAC pins are multiplexed with GPIO and UART
0325      * Further details are available at the DM365 ARM
0326      * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
0327      */
0328     davinci_cfg_reg(DM365_EMAC_TX_EN);
0329     davinci_cfg_reg(DM365_EMAC_TX_CLK);
0330     davinci_cfg_reg(DM365_EMAC_COL);
0331     davinci_cfg_reg(DM365_EMAC_TXD3);
0332     davinci_cfg_reg(DM365_EMAC_TXD2);
0333     davinci_cfg_reg(DM365_EMAC_TXD1);
0334     davinci_cfg_reg(DM365_EMAC_TXD0);
0335     davinci_cfg_reg(DM365_EMAC_RXD3);
0336     davinci_cfg_reg(DM365_EMAC_RXD2);
0337     davinci_cfg_reg(DM365_EMAC_RXD1);
0338     davinci_cfg_reg(DM365_EMAC_RXD0);
0339     davinci_cfg_reg(DM365_EMAC_RX_CLK);
0340     davinci_cfg_reg(DM365_EMAC_RX_DV);
0341     davinci_cfg_reg(DM365_EMAC_RX_ER);
0342     davinci_cfg_reg(DM365_EMAC_CRS);
0343     davinci_cfg_reg(DM365_EMAC_MDIO);
0344     davinci_cfg_reg(DM365_EMAC_MDCLK);
0345 
0346     /*
0347      * EMAC interrupts are multiplexed with GPIO interrupts
0348      * Details are available at the DM365 ARM
0349      * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
0350      */
0351     davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
0352     davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
0353     davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
0354     davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
0355 }
0356 
0357 static void dm365evm_mmc_configure(void)
0358 {
0359     /*
0360      * MMC/SD pins are multiplexed with GPIO and EMIF
0361      * Further details are available at the DM365 ARM
0362      * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
0363      */
0364     davinci_cfg_reg(DM365_SD1_CLK);
0365     davinci_cfg_reg(DM365_SD1_CMD);
0366     davinci_cfg_reg(DM365_SD1_DATA3);
0367     davinci_cfg_reg(DM365_SD1_DATA2);
0368     davinci_cfg_reg(DM365_SD1_DATA1);
0369     davinci_cfg_reg(DM365_SD1_DATA0);
0370 }
0371 
0372 static struct tvp514x_platform_data tvp5146_pdata = {
0373     .clk_polarity = 0,
0374     .hs_polarity = 1,
0375     .vs_polarity = 1
0376 };
0377 
0378 #define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
0379 /* Inputs available at the TVP5146 */
0380 static struct v4l2_input tvp5146_inputs[] = {
0381     {
0382         .index = 0,
0383         .name = "Composite",
0384         .type = V4L2_INPUT_TYPE_CAMERA,
0385         .std = TVP514X_STD_ALL,
0386     },
0387     {
0388         .index = 1,
0389         .name = "S-Video",
0390         .type = V4L2_INPUT_TYPE_CAMERA,
0391         .std = TVP514X_STD_ALL,
0392     },
0393 };
0394 
0395 /*
0396  * this is the route info for connecting each input to decoder
0397  * ouput that goes to vpfe. There is a one to one correspondence
0398  * with tvp5146_inputs
0399  */
0400 static struct vpfe_route tvp5146_routes[] = {
0401     {
0402         .input = INPUT_CVBS_VI2B,
0403         .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
0404     },
0405 {
0406         .input = INPUT_SVIDEO_VI2C_VI1C,
0407         .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
0408     },
0409 };
0410 
0411 static struct vpfe_subdev_info vpfe_sub_devs[] = {
0412     {
0413         .name = "tvp5146",
0414         .grp_id = 0,
0415         .num_inputs = ARRAY_SIZE(tvp5146_inputs),
0416         .inputs = tvp5146_inputs,
0417         .routes = tvp5146_routes,
0418         .can_route = 1,
0419         .ccdc_if_params = {
0420             .if_type = VPFE_BT656,
0421             .hdpol = VPFE_PINPOL_POSITIVE,
0422             .vdpol = VPFE_PINPOL_POSITIVE,
0423         },
0424         .board_info = {
0425             I2C_BOARD_INFO("tvp5146", 0x5d),
0426             .platform_data = &tvp5146_pdata,
0427         },
0428     },
0429 };
0430 
0431 static struct vpfe_config vpfe_cfg = {
0432     .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
0433     .sub_devs = vpfe_sub_devs,
0434     .i2c_adapter_id = 1,
0435     .card_name = "DM365 EVM",
0436     .ccdc = "ISIF",
0437 };
0438 
0439 /* venc standards timings */
0440 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
0441     {
0442         .name       = "ntsc",
0443         .timings_type   = VPBE_ENC_STD,
0444         .std_id     = V4L2_STD_NTSC,
0445         .interlaced = 1,
0446         .xres       = 720,
0447         .yres       = 480,
0448         .aspect     = {11, 10},
0449         .fps        = {30000, 1001},
0450         .left_margin    = 0x79,
0451         .upper_margin   = 0x10,
0452     },
0453     {
0454         .name       = "pal",
0455         .timings_type   = VPBE_ENC_STD,
0456         .std_id     = V4L2_STD_PAL,
0457         .interlaced = 1,
0458         .xres       = 720,
0459         .yres       = 576,
0460         .aspect     = {54, 59},
0461         .fps        = {25, 1},
0462         .left_margin    = 0x7E,
0463         .upper_margin   = 0x16,
0464     },
0465 };
0466 
0467 /* venc dv timings */
0468 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
0469     {
0470         .name       = "480p59_94",
0471         .timings_type   = VPBE_ENC_DV_TIMINGS,
0472         .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
0473         .interlaced = 0,
0474         .xres       = 720,
0475         .yres       = 480,
0476         .aspect     = {1, 1},
0477         .fps        = {5994, 100},
0478         .left_margin    = 0x8F,
0479         .upper_margin   = 0x2D,
0480     },
0481     {
0482         .name       = "576p50",
0483         .timings_type   = VPBE_ENC_DV_TIMINGS,
0484         .dv_timings = V4L2_DV_BT_CEA_720X576P50,
0485         .interlaced = 0,
0486         .xres       = 720,
0487         .yres       = 576,
0488         .aspect     = {1, 1},
0489         .fps        = {50, 1},
0490         .left_margin    = 0x8C,
0491         .upper_margin   = 0x36,
0492     },
0493     {
0494         .name       = "720p60",
0495         .timings_type   = VPBE_ENC_DV_TIMINGS,
0496         .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
0497         .interlaced = 0,
0498         .xres       = 1280,
0499         .yres       = 720,
0500         .aspect     = {1, 1},
0501         .fps        = {60, 1},
0502         .left_margin    = 0x117,
0503         .right_margin   = 70,
0504         .upper_margin   = 38,
0505         .lower_margin   = 3,
0506         .hsync_len  = 80,
0507         .vsync_len  = 5,
0508     },
0509     {
0510         .name       = "1080i60",
0511         .timings_type   = VPBE_ENC_DV_TIMINGS,
0512         .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
0513         .interlaced = 1,
0514         .xres       = 1920,
0515         .yres       = 1080,
0516         .aspect     = {1, 1},
0517         .fps        = {30, 1},
0518         .left_margin    = 0xc9,
0519         .right_margin   = 80,
0520         .upper_margin   = 30,
0521         .lower_margin   = 3,
0522         .hsync_len  = 88,
0523         .vsync_len  = 5,
0524     },
0525 };
0526 
0527 #define VENC_STD_ALL    (V4L2_STD_NTSC | V4L2_STD_PAL)
0528 
0529 /*
0530  * The outputs available from VPBE + ecnoders. Keep the
0531  * the order same as that of encoders. First those from venc followed by that
0532  * from encoders. Index in the output refers to index on a particular
0533  * encoder.Driver uses this index to pass it to encoder when it supports more
0534  * than one output. Application uses index of the array to set an output.
0535  */
0536 static struct vpbe_output dm365evm_vpbe_outputs[] = {
0537     {
0538         .output     = {
0539             .index      = 0,
0540             .name       = "Composite",
0541             .type       = V4L2_OUTPUT_TYPE_ANALOG,
0542             .std        = VENC_STD_ALL,
0543             .capabilities   = V4L2_OUT_CAP_STD,
0544         },
0545         .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
0546         .default_mode   = "ntsc",
0547         .num_modes  = ARRAY_SIZE(dm365evm_enc_std_timing),
0548         .modes      = dm365evm_enc_std_timing,
0549         .if_params  = MEDIA_BUS_FMT_FIXED,
0550     },
0551     {
0552         .output     = {
0553             .index      = 1,
0554             .name       = "Component",
0555             .type       = V4L2_OUTPUT_TYPE_ANALOG,
0556             .capabilities   = V4L2_OUT_CAP_DV_TIMINGS,
0557         },
0558         .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
0559         .default_mode   = "480p59_94",
0560         .num_modes  = ARRAY_SIZE(dm365evm_enc_preset_timing),
0561         .modes      = dm365evm_enc_preset_timing,
0562         .if_params  = MEDIA_BUS_FMT_FIXED,
0563     },
0564 };
0565 
0566 /*
0567  * Amplifiers on the board
0568  */
0569 static struct ths7303_platform_data ths7303_pdata = {
0570     .ch_1 = 3,
0571     .ch_2 = 3,
0572     .ch_3 = 3,
0573 };
0574 
0575 static struct amp_config_info vpbe_amp = {
0576     .module_name    = "ths7303",
0577     .is_i2c     = 1,
0578     .board_info = {
0579         I2C_BOARD_INFO("ths7303", 0x2c),
0580         .platform_data = &ths7303_pdata,
0581     }
0582 };
0583 
0584 static struct vpbe_config dm365evm_display_cfg = {
0585     .module_name    = "dm365-vpbe-display",
0586     .i2c_adapter_id = 1,
0587     .amp        = &vpbe_amp,
0588     .osd        = {
0589         .module_name    = DM365_VPBE_OSD_SUBDEV_NAME,
0590     },
0591     .venc       = {
0592         .module_name    = DM365_VPBE_VENC_SUBDEV_NAME,
0593     },
0594     .num_outputs    = ARRAY_SIZE(dm365evm_vpbe_outputs),
0595     .outputs    = dm365evm_vpbe_outputs,
0596 };
0597 
0598 static void __init evm_init_i2c(void)
0599 {
0600     davinci_init_i2c(&i2c_pdata);
0601     i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
0602 }
0603 
0604 static inline int have_leds(void)
0605 {
0606 #ifdef CONFIG_LEDS_CLASS
0607     return 1;
0608 #else
0609     return 0;
0610 #endif
0611 }
0612 
0613 struct cpld_led {
0614     struct led_classdev cdev;
0615     u8          mask;
0616 };
0617 
0618 static const struct {
0619     const char *name;
0620     const char *trigger;
0621 } cpld_leds[] = {
0622     { "dm365evm::ds2", },
0623     { "dm365evm::ds3", },
0624     { "dm365evm::ds4", },
0625     { "dm365evm::ds5", },
0626     { "dm365evm::ds6", "nand-disk", },
0627     { "dm365evm::ds7", "mmc1", },
0628     { "dm365evm::ds8", "mmc0", },
0629     { "dm365evm::ds9", "heartbeat", },
0630 };
0631 
0632 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
0633 {
0634     struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
0635     u8 reg = __raw_readb(cpld + CPLD_LEDS);
0636 
0637     if (b != LED_OFF)
0638         reg &= ~led->mask;
0639     else
0640         reg |= led->mask;
0641     __raw_writeb(reg, cpld + CPLD_LEDS);
0642 }
0643 
0644 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
0645 {
0646     struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
0647     u8 reg = __raw_readb(cpld + CPLD_LEDS);
0648 
0649     return (reg & led->mask) ? LED_OFF : LED_FULL;
0650 }
0651 
0652 static int __init cpld_leds_init(void)
0653 {
0654     int i;
0655 
0656     if (!have_leds() ||  !cpld)
0657         return 0;
0658 
0659     /* setup LEDs */
0660     __raw_writeb(0xff, cpld + CPLD_LEDS);
0661     for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
0662         struct cpld_led *led;
0663 
0664         led = kzalloc(sizeof(*led), GFP_KERNEL);
0665         if (!led)
0666             break;
0667 
0668         led->cdev.name = cpld_leds[i].name;
0669         led->cdev.brightness_set = cpld_led_set;
0670         led->cdev.brightness_get = cpld_led_get;
0671         led->cdev.default_trigger = cpld_leds[i].trigger;
0672         led->mask = BIT(i);
0673 
0674         if (led_classdev_register(NULL, &led->cdev) < 0) {
0675             kfree(led);
0676             break;
0677         }
0678     }
0679 
0680     return 0;
0681 }
0682 /* run after subsys_initcall() for LEDs */
0683 fs_initcall(cpld_leds_init);
0684 
0685 
0686 static void __init evm_init_cpld(void)
0687 {
0688     u8 mux, resets;
0689     const char *label;
0690     struct clk *aemif_clk;
0691     int rc;
0692 
0693     /* Make sure we can configure the CPLD through CS1.  Then
0694      * leave it on for later access to MMC and LED registers.
0695      */
0696     aemif_clk = clk_get(NULL, "aemif");
0697     if (IS_ERR(aemif_clk))
0698         return;
0699     clk_prepare_enable(aemif_clk);
0700 
0701     if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
0702             "cpld") == NULL)
0703         goto fail;
0704     cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
0705     if (!cpld) {
0706         release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
0707                 SECTION_SIZE);
0708 fail:
0709         pr_err("ERROR: can't map CPLD\n");
0710         clk_disable_unprepare(aemif_clk);
0711         return;
0712     }
0713 
0714     /* External muxing for some signals */
0715     mux = 0;
0716 
0717     /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
0718      * NOTE:  SW4 bus width setting must match!
0719      */
0720     if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
0721         /* external keypad mux */
0722         mux |= BIT(7);
0723 
0724         rc = platform_device_register(&davinci_aemif_device);
0725         if (rc)
0726             pr_warn("%s(): error registering the aemif device: %d\n",
0727                 __func__, rc);
0728     } else {
0729         /* no OneNAND support yet */
0730     }
0731 
0732     /* Leave external chips in reset when unused. */
0733     resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
0734 
0735     /* Static video input config with SN74CBT16214 1-of-3 mux:
0736      *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
0737      *  - port b2 == imager (mux lowbits == 2 or 7)
0738      *  - port b3 == tvp5146 (mux lowbits == 5)
0739      *
0740      * Runtime switching could work too, with limitations.
0741      */
0742     if (have_imager()) {
0743         label = "HD imager";
0744         mux |= 2;
0745 
0746         /* externally mux MMC1/ENET/AIC33 to imager */
0747         mux |= BIT(6) | BIT(5) | BIT(3);
0748     } else {
0749         struct davinci_soc_info *soc_info = &davinci_soc_info;
0750 
0751         /* we can use MMC1 ... */
0752         dm365evm_mmc_configure();
0753         davinci_setup_mmc(1, &dm365evm_mmc_config);
0754 
0755         /* ... and ENET ... */
0756         dm365evm_emac_configure();
0757         soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
0758         resets &= ~BIT(3);
0759 
0760         /* ... and AIC33 */
0761         resets &= ~BIT(1);
0762 
0763         if (have_tvp7002()) {
0764             mux |= 1;
0765             resets &= ~BIT(2);
0766             label = "tvp7002 HD";
0767         } else {
0768             /* default to tvp5146 */
0769             mux |= 5;
0770             resets &= ~BIT(0);
0771             label = "tvp5146 SD";
0772         }
0773     }
0774     __raw_writeb(mux, cpld + CPLD_MUX);
0775     __raw_writeb(resets, cpld + CPLD_RESETS);
0776     pr_info("EVM: %s video input\n", label);
0777 
0778     /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
0779 }
0780 
0781 static void __init dm365_evm_map_io(void)
0782 {
0783     dm365_init();
0784 }
0785 
0786 static struct spi_eeprom at25640 = {
0787     .byte_len   = SZ_64K / 8,
0788     .name       = "at25640",
0789     .page_size  = 32,
0790     .flags      = EE_ADDR2,
0791 };
0792 
0793 static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
0794     {
0795         .modalias   = "at25",
0796         .platform_data  = &at25640,
0797         .max_speed_hz   = 10 * 1000 * 1000,
0798         .bus_num    = 0,
0799         .chip_select    = 0,
0800         .mode       = SPI_MODE_0,
0801     },
0802 };
0803 
0804 static __init void dm365_evm_init(void)
0805 {
0806     int ret;
0807 
0808     dm365_register_clocks();
0809 
0810     ret = dm365_gpio_register();
0811     if (ret)
0812         pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
0813 
0814     regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
0815                      ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
0816     regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
0817                      ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
0818 
0819     nvmem_add_cell_table(&davinci_nvmem_cell_table);
0820     nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
0821 
0822     evm_init_i2c();
0823     davinci_serial_init(dm365_serial_device);
0824 
0825     dm365evm_emac_configure();
0826     dm365evm_mmc_configure();
0827 
0828     davinci_setup_mmc(0, &dm365evm_mmc_config);
0829 
0830     dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
0831 
0832     /* maybe setup mmc1/etc ... _after_ mmc0 */
0833     evm_init_cpld();
0834 
0835 #ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
0836     dm365_init_asp();
0837 #elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
0838     dm365_init_vc();
0839 #endif
0840     dm365_init_rtc();
0841     dm365_init_ks(&dm365evm_ks_data);
0842 
0843     dm365_init_spi0(BIT(0), dm365_evm_spi_info,
0844             ARRAY_SIZE(dm365_evm_spi_info));
0845 }
0846 
0847 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
0848     .atag_offset    = 0x100,
0849     .map_io     = dm365_evm_map_io,
0850     .init_irq   = dm365_init_irq,
0851     .init_time  = dm365_init_time,
0852     .init_machine   = dm365_evm_init,
0853     .init_late  = davinci_init_late,
0854     .dma_zone_size  = SZ_128M,
0855 MACHINE_END
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