arm/mach-cns3xxx/pcie.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * PCI-E support for CNS3xxx
0004  *
0005  * Copyright 2008 Cavium Networks
0006  *        Richard Liu <richard.liu@caviumnetworks.com>
0007  * Copyright 2010 MontaVista Software, LLC.
0008  *        Anton Vorontsov <avorontsov@mvista.com>
0009  */
0010
0011 #include <linux/init.h>
0012 #include <linux/kernel.h>
0013 #include <linux/bug.h>
0014 #include <linux/pci.h>
0015 #include <linux/io.h>
0016 #include <linux/ioport.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/ptrace.h>
0019 #include <asm/mach/map.h>
0020 #include "cns3xxx.h"
0021 #include "core.h"
0022
0023 struct cns3xxx_pcie {
0024     void __iomem *host_regs; /* PCI config registers for host bridge */
0025     void __iomem *cfg0_regs; /* PCI Type 0 config registers */
0026     void __iomem *cfg1_regs; /* PCI Type 1 config registers */
0027     unsigned int irqs[2];
0028     struct resource res_io;
0029     struct resource res_mem;
0030     int port;
0031     bool linked;
0032 };
0033
0034 static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
0035 {
0036     struct pci_sys_data *root = sysdata;
0037
0038     return root->private_data;
0039 }
0040
0041 static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
0042 {
0043     return sysdata_to_cnspci(dev->sysdata);
0044 }
0045
0046 static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
0047 {
0048     return sysdata_to_cnspci(bus->sysdata);
0049 }
0050
0051 static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
0052                      unsigned int devfn, int where)
0053 {
0054     struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
0055     int busno = bus->number;
0056     int slot = PCI_SLOT(devfn);
0057     void __iomem *base;
0058
0059     /* If there is no link, just show the CNS PCI bridge. */
0060     if (!cnspci->linked && busno > 0)
0061         return NULL;
0062
0063     /*
0064      * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
0065      * we still want to access it.
0066      * We place the host bridge on bus 0, and the directly connected
0067      * device on bus 1, slot 0.
0068      */
0069     if (busno == 0) { /* internal PCIe bus, host bridge device */
0070         if (devfn == 0) /* device# and function# are ignored by hw */
0071             base = cnspci->host_regs;
0072         else
0073             return NULL; /* no such device */
0074
0075     } else if (busno == 1) { /* directly connected PCIe device */
0076         if (slot == 0) /* device# is ignored by hw */
0077             base = cnspci->cfg0_regs;
0078         else
0079             return NULL; /* no such device */
0080     } else /* remote PCI bus */
0081         base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
0082
0083     return base + where + (devfn << 12);
0084 }
0085
0086 static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
0087                    int where, int size, u32 *val)
0088 {
0089     int ret;
0090     u32 mask = (0x1ull << (size * 8)) - 1;
0091     int shift = (where % 4) * 8;
0092
0093     ret = pci_generic_config_read(bus, devfn, where, size, val);
0094
0095     if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
0096         (where & 0xffc) == PCI_CLASS_REVISION)
0097         /*
0098          * RC's class is 0xb, but Linux PCI driver needs 0x604
0099          * for a PCIe bridge. So we must fixup the class code
0100          * to 0x604 here.
0101          */
0102         *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask;
0103
0104     return ret;
0105 }
0106
0107 static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
0108 {
0109     struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
0110     struct resource *res_io = &cnspci->res_io;
0111     struct resource *res_mem = &cnspci->res_mem;
0112
0113     BUG_ON(request_resource(&iomem_resource, res_io) ||
0114            request_resource(&iomem_resource, res_mem));
0115
0116     pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
0117     pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
0118
0119     return 1;
0120 }
0121
0122 static struct pci_ops cns3xxx_pcie_ops = {
0123     .map_bus = cns3xxx_pci_map_bus,
0124     .read = cns3xxx_pci_read_config,
0125     .write = pci_generic_config_write,
0126 };
0127
0128 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0129 {
0130     struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
0131     int irq = cnspci->irqs[!!dev->bus->number];
0132
0133     pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
0134         pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
0135         PCI_FUNC(dev->devfn), slot, pin, irq);
0136
0137     return irq;
0138 }
0139
0140 static struct cns3xxx_pcie cns3xxx_pcie[] = {
0141     [0] = {
0142         .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
0143         .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
0144         .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
0145         .res_io = {
0146             .name = "PCIe0 I/O space",
0147             .start = CNS3XXX_PCIE0_IO_BASE,
0148             .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
0149             .flags = IORESOURCE_IO,
0150         },
0151         .res_mem = {
0152             .name = "PCIe0 non-prefetchable",
0153             .start = CNS3XXX_PCIE0_MEM_BASE,
0154             .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
0155             .flags = IORESOURCE_MEM,
0156         },
0157         .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
0158         .port = 0,
0159     },
0160     [1] = {
0161         .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
0162         .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
0163         .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
0164         .res_io = {
0165             .name = "PCIe1 I/O space",
0166             .start = CNS3XXX_PCIE1_IO_BASE,
0167             .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
0168             .flags = IORESOURCE_IO,
0169         },
0170         .res_mem = {
0171             .name = "PCIe1 non-prefetchable",
0172             .start = CNS3XXX_PCIE1_MEM_BASE,
0173             .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
0174             .flags = IORESOURCE_MEM,
0175         },
0176         .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
0177         .port = 1,
0178     },
0179 };
0180
0181 static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
0182 {
0183     int port = cnspci->port;
0184     u32 reg;
0185     unsigned long time;
0186
0187     reg = __raw_readl(MISC_PCIE_CTRL(port));
0188     /*
0189      * Enable Application Request to 1, it will exit L1 automatically,
0190      * but when chip back, it will use another clock, still can use 0x1.
0191      */
0192     reg |= 0x3;
0193     __raw_writel(reg, MISC_PCIE_CTRL(port));
0194
0195     pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
0196     pr_info("PCIe: Port[%d] Check data link layer...", port);
0197
0198     time = jiffies;
0199     while (1) {
0200         reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
0201         if (reg & 0x1) {
0202             pr_info("Link up.\n");
0203             cnspci->linked = 1;
0204             break;
0205         } else if (time_after(jiffies, time + 50)) {
0206             pr_info("Device not found.\n");
0207             break;
0208         }
0209     }
0210 }
0211
0212 static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci,
0213                      int where, int size, u32 val)
0214 {
0215     void __iomem *base = cnspci->host_regs + (where & 0xffc);
0216     u32 v;
0217     u32 mask = (0x1ull << (size * 8)) - 1;
0218     int shift = (where % 4) * 8;
0219
0220     v = readl_relaxed(base);
0221
0222     v &= ~(mask << shift);
0223     v |= (val & mask) << shift;
0224
0225     writel_relaxed(v, base);
0226     readl_relaxed(base);
0227 }
0228
0229 static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
0230 {
0231     u16 mem_base  = cnspci->res_mem.start >> 16;
0232     u16 mem_limit = cnspci->res_mem.end   >> 16;
0233     u16 io_base   = cnspci->res_io.start  >> 16;
0234     u16 io_limit  = cnspci->res_io.end    >> 16;
0235
0236     cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0);
0237     cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1);
0238     cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1);
0239     cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base);
0240     cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit);
0241     cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
0242     cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit);
0243
0244     if (!cnspci->linked)
0245         return;
0246
0247     /* Set Device Max_Read_Request_Size to 128 byte */
0248     pcie_bus_config = PCIE_BUS_PEER2PEER;
0249
0250     /* Disable PCIe0 Interrupt Mask INTA to INTD */
0251     __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));
0252 }
0253
0254 static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
0255                       struct pt_regs *regs)
0256 {
0257     if (fsr & (1 << 10))
0258         regs->ARM_pc += 4;
0259     return 0;
0260 }
0261
0262 void __init cns3xxx_pcie_init_late(void)
0263 {
0264     int i;
0265     void *private_data;
0266     struct hw_pci hw_pci = {
0267            .nr_controllers = 1,
0268            .ops = &cns3xxx_pcie_ops,
0269            .setup = cns3xxx_pci_setup,
0270            .map_irq = cns3xxx_pcie_map_irq,
0271            .private_data = &private_data,
0272     };
0273
0274     pcibios_min_io = 0;
0275     pcibios_min_mem = 0;
0276
0277     hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
0278             "imprecise external abort");
0279
0280     for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
0281         cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
0282         cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
0283         cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
0284         cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
0285         private_data = &cns3xxx_pcie[i];
0286         pci_common_init(&hw_pci);
0287     }
0288
0289     pci_assign_unassigned_resources();
0290 }