arm/mach-cns3xxx/devices.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * CNS3xxx common devices
0004  *
0005  * Copyright 2008 Cavium Networks
0006  *        Scott Shu
0007  * Copyright 2010 MontaVista Software, LLC.
0008  *        Anton Vorontsov <avorontsov@mvista.com>
0009  */
0010
0011 #include <linux/io.h>
0012 #include <linux/init.h>
0013 #include <linux/compiler.h>
0014 #include <linux/dma-mapping.h>
0015 #include <linux/platform_device.h>
0016 #include "cns3xxx.h"
0017 #include "pm.h"
0018 #include "core.h"
0019 #include "devices.h"
0020
0021 /*
0022  * AHCI
0023  */
0024 static struct resource cns3xxx_ahci_resource[] = {
0025     [0] = {
0026         .start  = CNS3XXX_SATA2_BASE,
0027         .end    = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
0028         .flags  = IORESOURCE_MEM,
0029     },
0030     [1] = {
0031         .start  = IRQ_CNS3XXX_SATA,
0032         .end    = IRQ_CNS3XXX_SATA,
0033         .flags  = IORESOURCE_IRQ,
0034     },
0035 };
0036
0037 static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
0038
0039 static struct platform_device cns3xxx_ahci_pdev = {
0040     .name       = "ahci",
0041     .id     = 0,
0042     .resource   = cns3xxx_ahci_resource,
0043     .num_resources  = ARRAY_SIZE(cns3xxx_ahci_resource),
0044     .dev        = {
0045         .dma_mask       = &cns3xxx_ahci_dmamask,
0046         .coherent_dma_mask  = DMA_BIT_MASK(32),
0047     },
0048 };
0049
0050 void __init cns3xxx_ahci_init(void)
0051 {
0052     u32 tmp;
0053
0054     tmp = __raw_readl(MISC_SATA_POWER_MODE);
0055     tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
0056     tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
0057     __raw_writel(tmp, MISC_SATA_POWER_MODE);
0058
0059     /* Enable SATA PHY */
0060     cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
0061     cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
0062
0063     /* Enable SATA Clock */
0064     cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
0065
0066     /* De-Asscer SATA Reset */
0067     cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
0068
0069     platform_device_register(&cns3xxx_ahci_pdev);
0070 }
0071
0072 /*
0073  * SDHCI
0074  */
0075 static struct resource cns3xxx_sdhci_resources[] = {
0076     [0] = {
0077         .start = CNS3XXX_SDIO_BASE,
0078         .end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
0079         .flags = IORESOURCE_MEM,
0080     },
0081     [1] = {
0082         .start = IRQ_CNS3XXX_SDIO,
0083         .end   = IRQ_CNS3XXX_SDIO,
0084         .flags = IORESOURCE_IRQ,
0085     },
0086 };
0087
0088 static struct platform_device cns3xxx_sdhci_pdev = {
0089     .name       = "sdhci-cns3xxx",
0090     .id     = 0,
0091     .num_resources  = ARRAY_SIZE(cns3xxx_sdhci_resources),
0092     .resource   = cns3xxx_sdhci_resources,
0093 };
0094
0095 void __init cns3xxx_sdhci_init(void)
0096 {
0097     u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
0098     u32 gpioa_pins = __raw_readl(gpioa);
0099
0100     /* MMC/SD pins share with GPIOA */
0101     gpioa_pins |= 0x1fff0004;
0102     __raw_writel(gpioa_pins, gpioa);
0103
0104     cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
0105     cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
0106
0107     platform_device_register(&cns3xxx_sdhci_pdev);
0108 }