arm/mach-bcm/platsmp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2014-2015 Broadcom Corporation
0004  * Copyright 2014 Linaro Limited
0005  */
0006
0007 #include <linux/cpumask.h>
0008 #include <linux/delay.h>
0009 #include <linux/errno.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/irqchip/irq-bcm2836.h>
0013 #include <linux/jiffies.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/sched.h>
0017 #include <linux/sched/clock.h>
0018 #include <linux/smp.h>
0019
0020 #include <asm/cacheflush.h>
0021 #include <asm/smp.h>
0022 #include <asm/smp_plat.h>
0023 #include <asm/smp_scu.h>
0024
0025 #include "platsmp.h"
0026
0027 /* Size of mapped Cortex A9 SCU address space */
0028 #define CORTEX_A9_SCU_SIZE  0x58
0029
0030 #define SECONDARY_TIMEOUT_NS    NSEC_PER_MSEC   /* 1 msec (in nanoseconds) */
0031 #define BOOT_ADDR_CPUID_MASK    0x3
0032
0033 /* Name of device node property defining secondary boot register location */
0034 #define OF_SECONDARY_BOOT   "secondary-boot-reg"
0035 #define MPIDR_CPUID_BITMASK 0x3
0036
0037 /*
0038  * Enable the Cortex A9 Snoop Control Unit
0039  *
0040  * By the time this is called we already know there are multiple
0041  * cores present.  We assume we're running on a Cortex A9 processor,
0042  * so any trouble getting the base address register or getting the
0043  * SCU base is a problem.
0044  *
0045  * Return 0 if successful or an error code otherwise.
0046  */
0047 static int __init scu_a9_enable(void)
0048 {
0049     unsigned long config_base;
0050     void __iomem *scu_base;
0051
0052     if (!scu_a9_has_base()) {
0053         pr_err("no configuration base address register!\n");
0054         return -ENXIO;
0055     }
0056
0057     /* Config base address register value is zero for uniprocessor */
0058     config_base = scu_a9_get_base();
0059     if (!config_base) {
0060         pr_err("hardware reports only one core\n");
0061         return -ENOENT;
0062     }
0063
0064     scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
0065     if (!scu_base) {
0066         pr_err("failed to remap config base (%lu/%u) for SCU\n",
0067             config_base, CORTEX_A9_SCU_SIZE);
0068         return -ENOMEM;
0069     }
0070
0071     scu_enable(scu_base);
0072
0073     iounmap(scu_base);  /* That's the last we'll need of this */
0074
0075     return 0;
0076 }
0077
0078 static u32 secondary_boot_addr_for(unsigned int cpu)
0079 {
0080     u32 secondary_boot_addr = 0;
0081     struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
0082
0083         if (!cpu_node) {
0084         pr_err("Failed to find device tree node for CPU%u\n", cpu);
0085         return 0;
0086     }
0087
0088     if (of_property_read_u32(cpu_node,
0089                  OF_SECONDARY_BOOT,
0090                  &secondary_boot_addr))
0091         pr_err("required secondary boot register not specified for CPU%u\n",
0092             cpu);
0093
0094     of_node_put(cpu_node);
0095
0096     return secondary_boot_addr;
0097 }
0098
0099 static int nsp_write_lut(unsigned int cpu)
0100 {
0101     void __iomem *sku_rom_lut;
0102     phys_addr_t secondary_startup_phy;
0103     const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
0104
0105     if (!secondary_boot_addr)
0106         return -EINVAL;
0107
0108     sku_rom_lut = ioremap((phys_addr_t)secondary_boot_addr,
0109                       sizeof(phys_addr_t));
0110     if (!sku_rom_lut) {
0111         pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
0112         return -ENOMEM;
0113     }
0114
0115     secondary_startup_phy = __pa_symbol(secondary_startup);
0116     BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
0117
0118     writel_relaxed(secondary_startup_phy, sku_rom_lut);
0119
0120     /* Ensure the write is visible to the secondary core */
0121     smp_wmb();
0122
0123     iounmap(sku_rom_lut);
0124
0125     return 0;
0126 }
0127
0128 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
0129 {
0130     const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
0131
0132     /* Enable the SCU on Cortex A9 based SoCs */
0133     if (scu_a9_enable()) {
0134         /* Update the CPU present map to reflect uniprocessor mode */
0135         pr_warn("failed to enable A9 SCU - disabling SMP\n");
0136         init_cpu_present(&only_cpu_0);
0137     }
0138 }
0139
0140 /*
0141  * The ROM code has the secondary cores looping, waiting for an event.
0142  * When an event occurs each core examines the bottom two bits of the
0143  * secondary boot register.  When a core finds those bits contain its
0144  * own core id, it performs initialization, including computing its boot
0145  * address by clearing the boot register value's bottom two bits.  The
0146  * core signals that it is beginning its execution by writing its boot
0147  * address back to the secondary boot register, and finally jumps to
0148  * that address.
0149  *
0150  * So to start a core executing we need to:
0151  * - Encode the (hardware) CPU id with the bottom bits of the secondary
0152  *   start address.
0153  * - Write that value into the secondary boot register.
0154  * - Generate an event to wake up the secondary CPU(s).
0155  * - Wait for the secondary boot register to be re-written, which
0156  *   indicates the secondary core has started.
0157  */
0158 static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
0159 {
0160     void __iomem *boot_reg;
0161     phys_addr_t boot_func;
0162     u64 start_clock;
0163     u32 cpu_id;
0164     u32 boot_val;
0165     bool timeout = false;
0166     const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
0167
0168     cpu_id = cpu_logical_map(cpu);
0169     if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
0170         pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
0171         return -EINVAL;
0172     }
0173
0174     if (!secondary_boot_addr)
0175         return -EINVAL;
0176
0177     boot_reg = ioremap((phys_addr_t)secondary_boot_addr,
0178                    sizeof(phys_addr_t));
0179     if (!boot_reg) {
0180         pr_err("unable to map boot register for cpu %u\n", cpu_id);
0181         return -ENOMEM;
0182     }
0183
0184     /*
0185      * Secondary cores will start in secondary_startup(),
0186      * defined in "arch/arm/kernel/head.S"
0187      */
0188     boot_func = __pa_symbol(secondary_startup);
0189     BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
0190     BUG_ON(boot_func > (phys_addr_t)U32_MAX);
0191
0192     /* The core to start is encoded in the low bits */
0193     boot_val = (u32)boot_func | cpu_id;
0194     writel_relaxed(boot_val, boot_reg);
0195
0196     sev();
0197
0198     /* The low bits will be cleared once the core has started */
0199     start_clock = local_clock();
0200     while (!timeout && readl_relaxed(boot_reg) == boot_val)
0201         timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
0202
0203     iounmap(boot_reg);
0204
0205     if (!timeout)
0206         return 0;
0207
0208     pr_err("timeout waiting for cpu %u to start\n", cpu_id);
0209
0210     return -ENXIO;
0211 }
0212
0213 /* Cluster Dormant Control command to bring CPU into a running state */
0214 #define CDC_CMD         6
0215 #define CDC_CMD_OFFSET      0
0216 #define CDC_CMD_REG(cpu)    (CDC_CMD_OFFSET + 4*(cpu))
0217
0218 /*
0219  * BCM23550 has a Cluster Dormant Control block that keeps the core in
0220  * idle state. A command needs to be sent to the block to bring the CPU
0221  * into running state.
0222  */
0223 static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle)
0224 {
0225     void __iomem *cdc_base;
0226     struct device_node *dn;
0227     char *name;
0228     int ret;
0229
0230     /* Make sure a CDC node exists before booting the
0231      * secondary core.
0232      */
0233     name = "brcm,bcm23550-cdc";
0234     dn = of_find_compatible_node(NULL, NULL, name);
0235     if (!dn) {
0236         pr_err("unable to find cdc node\n");
0237         return -ENODEV;
0238     }
0239
0240     cdc_base = of_iomap(dn, 0);
0241     of_node_put(dn);
0242
0243     if (!cdc_base) {
0244         pr_err("unable to remap cdc base register\n");
0245         return -ENOMEM;
0246     }
0247
0248     /* Boot the secondary core */
0249     ret = kona_boot_secondary(cpu, idle);
0250     if (ret)
0251         goto out;
0252
0253     /* Bring this CPU to RUN state so that nIRQ nFIQ
0254      * signals are unblocked.
0255      */
0256     writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu));
0257
0258 out:
0259     iounmap(cdc_base);
0260
0261     return ret;
0262 }
0263
0264 static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
0265 {
0266     int ret;
0267
0268     /*
0269      * After wake up, secondary core branches to the startup
0270      * address programmed at SKU ROM LUT location.
0271      */
0272     ret = nsp_write_lut(cpu);
0273     if (ret) {
0274         pr_err("unable to write startup addr to SKU ROM LUT\n");
0275         goto out;
0276     }
0277
0278     /* Send a CPU wakeup interrupt to the secondary core */
0279     arch_send_wakeup_ipi_mask(cpumask_of(cpu));
0280
0281 out:
0282     return ret;
0283 }
0284
0285 static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle)
0286 {
0287     void __iomem *intc_base;
0288     struct device_node *dn;
0289     char *name;
0290
0291     name = "brcm,bcm2836-l1-intc";
0292     dn = of_find_compatible_node(NULL, NULL, name);
0293     if (!dn) {
0294         pr_err("unable to find intc node\n");
0295         return -ENODEV;
0296     }
0297
0298     intc_base = of_iomap(dn, 0);
0299     of_node_put(dn);
0300
0301     if (!intc_base) {
0302         pr_err("unable to remap intc base register\n");
0303         return -ENOMEM;
0304     }
0305
0306     writel(virt_to_phys(secondary_startup),
0307            intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
0308
0309     dsb(sy);
0310     sev();
0311
0312     iounmap(intc_base);
0313
0314     return 0;
0315 }
0316
0317 static const struct smp_operations kona_smp_ops __initconst = {
0318     .smp_prepare_cpus   = bcm_smp_prepare_cpus,
0319     .smp_boot_secondary = kona_boot_secondary,
0320 };
0321 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
0322             &kona_smp_ops);
0323
0324 static const struct smp_operations bcm23550_smp_ops __initconst = {
0325     .smp_boot_secondary = bcm23550_boot_secondary,
0326 };
0327 CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550",
0328             &bcm23550_smp_ops);
0329
0330 static const struct smp_operations nsp_smp_ops __initconst = {
0331     .smp_prepare_cpus   = bcm_smp_prepare_cpus,
0332     .smp_boot_secondary = nsp_boot_secondary,
0333 };
0334 CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
0335
0336 const struct smp_operations bcm2836_smp_ops __initconst = {
0337     .smp_boot_secondary = bcm2836_boot_secondary,
0338 };
0339 CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops);