arm/mach-bcm/platsmp-brcmstb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Broadcom STB CPU SMP and hotplug support for ARM
0004  *
0005  * Copyright (C) 2013-2014 Broadcom Corporation
0006  */
0007
0008 #include <linux/delay.h>
0009 #include <linux/errno.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/jiffies.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/printk.h>
0016 #include <linux/regmap.h>
0017 #include <linux/smp.h>
0018 #include <linux/mfd/syscon.h>
0019
0020 #include <asm/cacheflush.h>
0021 #include <asm/cp15.h>
0022 #include <asm/mach-types.h>
0023 #include <asm/smp_plat.h>
0024
0025 enum {
0026     ZONE_MAN_CLKEN_MASK     = BIT(0),
0027     ZONE_MAN_RESET_CNTL_MASK    = BIT(1),
0028     ZONE_MAN_MEM_PWR_MASK       = BIT(4),
0029     ZONE_RESERVED_1_MASK        = BIT(5),
0030     ZONE_MAN_ISO_CNTL_MASK      = BIT(6),
0031     ZONE_MANUAL_CONTROL_MASK    = BIT(7),
0032     ZONE_PWR_DN_REQ_MASK        = BIT(9),
0033     ZONE_PWR_UP_REQ_MASK        = BIT(10),
0034     ZONE_BLK_RST_ASSERT_MASK    = BIT(12),
0035     ZONE_PWR_OFF_STATE_MASK     = BIT(25),
0036     ZONE_PWR_ON_STATE_MASK      = BIT(26),
0037     ZONE_DPG_PWR_STATE_MASK     = BIT(28),
0038     ZONE_MEM_PWR_STATE_MASK     = BIT(29),
0039     ZONE_RESET_STATE_MASK       = BIT(31),
0040     CPU0_PWR_ZONE_CTRL_REG      = 1,
0041     CPU_RESET_CONFIG_REG        = 2,
0042 };
0043
0044 static void __iomem *cpubiuctrl_block;
0045 static void __iomem *hif_cont_block;
0046 static u32 cpu0_pwr_zone_ctrl_reg;
0047 static u32 cpu_rst_cfg_reg;
0048 static u32 hif_cont_reg;
0049
0050 #ifdef CONFIG_HOTPLUG_CPU
0051 /*
0052  * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
0053  * one or more cache may be disabled, we must flush to ensure coherency. We
0054  * cannot use traditional completion structures or spinlocks as they rely on
0055  * coherency.
0056  */
0057 static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
0058
0059 static int per_cpu_sw_state_rd(u32 cpu)
0060 {
0061     sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
0062     return per_cpu(per_cpu_sw_state, cpu);
0063 }
0064
0065 static void per_cpu_sw_state_wr(u32 cpu, int val)
0066 {
0067     dmb();
0068     per_cpu(per_cpu_sw_state, cpu) = val;
0069     sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
0070 }
0071 #else
0072 static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
0073 #endif
0074
0075 static void __iomem *pwr_ctrl_get_base(u32 cpu)
0076 {
0077     void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
0078     base += (cpu_logical_map(cpu) * 4);
0079     return base;
0080 }
0081
0082 static u32 pwr_ctrl_rd(u32 cpu)
0083 {
0084     void __iomem *base = pwr_ctrl_get_base(cpu);
0085     return readl_relaxed(base);
0086 }
0087
0088 static void pwr_ctrl_set(unsigned int cpu, u32 val, u32 mask)
0089 {
0090     void __iomem *base = pwr_ctrl_get_base(cpu);
0091     writel((readl(base) & mask) | val, base);
0092 }
0093
0094 static void pwr_ctrl_clr(unsigned int cpu, u32 val, u32 mask)
0095 {
0096     void __iomem *base = pwr_ctrl_get_base(cpu);
0097     writel((readl(base) & mask) & ~val, base);
0098 }
0099
0100 #define POLL_TMOUT_MS 500
0101 static int pwr_ctrl_wait_tmout(unsigned int cpu, u32 set, u32 mask)
0102 {
0103     const unsigned long timeo = jiffies + msecs_to_jiffies(POLL_TMOUT_MS);
0104     u32 tmp;
0105
0106     do {
0107         tmp = pwr_ctrl_rd(cpu) & mask;
0108         if (!set == !tmp)
0109             return 0;
0110     } while (time_before(jiffies, timeo));
0111
0112     tmp = pwr_ctrl_rd(cpu) & mask;
0113     if (!set == !tmp)
0114         return 0;
0115
0116     return -ETIMEDOUT;
0117 }
0118
0119 static void cpu_rst_cfg_set(u32 cpu, int set)
0120 {
0121     u32 val;
0122     val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
0123     if (set)
0124         val |= BIT(cpu_logical_map(cpu));
0125     else
0126         val &= ~BIT(cpu_logical_map(cpu));
0127     writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
0128 }
0129
0130 static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
0131 {
0132     const int reg_ofs = cpu_logical_map(cpu) * 8;
0133     writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
0134     writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
0135 }
0136
0137 static void brcmstb_cpu_boot(u32 cpu)
0138 {
0139     /* Mark this CPU as "up" */
0140     per_cpu_sw_state_wr(cpu, 1);
0141
0142     /*
0143      * Set the reset vector to point to the secondary_startup
0144      * routine
0145      */
0146     cpu_set_boot_addr(cpu, __pa_symbol(secondary_startup));
0147
0148     /* Unhalt the cpu */
0149     cpu_rst_cfg_set(cpu, 0);
0150 }
0151
0152 static void brcmstb_cpu_power_on(u32 cpu)
0153 {
0154     /*
0155      * The secondary cores power was cut, so we must go through
0156      * power-on initialization.
0157      */
0158     pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, 0xffffff00);
0159     pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
0160     pwr_ctrl_set(cpu, ZONE_RESERVED_1_MASK, -1);
0161
0162     pwr_ctrl_set(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
0163
0164     if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_MEM_PWR_STATE_MASK))
0165         panic("ZONE_MEM_PWR_STATE_MASK set timeout");
0166
0167     pwr_ctrl_set(cpu, ZONE_MAN_CLKEN_MASK, -1);
0168
0169     if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_DPG_PWR_STATE_MASK))
0170         panic("ZONE_DPG_PWR_STATE_MASK set timeout");
0171
0172     pwr_ctrl_clr(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
0173     pwr_ctrl_set(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
0174 }
0175
0176 static int brcmstb_cpu_get_power_state(u32 cpu)
0177 {
0178     int tmp = pwr_ctrl_rd(cpu);
0179     return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
0180 }
0181
0182 #ifdef CONFIG_HOTPLUG_CPU
0183
0184 static void brcmstb_cpu_die(u32 cpu)
0185 {
0186     v7_exit_coherency_flush(all);
0187
0188     per_cpu_sw_state_wr(cpu, 0);
0189
0190     /* Sit and wait to die */
0191     wfi();
0192
0193     /* We should never get here... */
0194     while (1)
0195         ;
0196 }
0197
0198 static int brcmstb_cpu_kill(u32 cpu)
0199 {
0200     /*
0201      * Ordinarily, the hardware forbids power-down of CPU0 (which is good
0202      * because it is the boot CPU), but this is not true when using BPCM
0203      * manual mode.  Consequently, we must avoid turning off CPU0 here to
0204      * ensure that TI2C master reset will work.
0205      */
0206     if (cpu == 0) {
0207         pr_warn("SMP: refusing to power off CPU0\n");
0208         return 1;
0209     }
0210
0211     while (per_cpu_sw_state_rd(cpu))
0212         ;
0213
0214     pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
0215     pwr_ctrl_clr(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
0216     pwr_ctrl_clr(cpu, ZONE_MAN_CLKEN_MASK, -1);
0217     pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
0218     pwr_ctrl_clr(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
0219
0220     if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_MEM_PWR_STATE_MASK))
0221         panic("ZONE_MEM_PWR_STATE_MASK clear timeout");
0222
0223     pwr_ctrl_clr(cpu, ZONE_RESERVED_1_MASK, -1);
0224
0225     if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_DPG_PWR_STATE_MASK))
0226         panic("ZONE_DPG_PWR_STATE_MASK clear timeout");
0227
0228     /* Flush pipeline before resetting CPU */
0229     mb();
0230
0231     /* Assert reset on the CPU */
0232     cpu_rst_cfg_set(cpu, 1);
0233
0234     return 1;
0235 }
0236
0237 #endif /* CONFIG_HOTPLUG_CPU */
0238
0239 static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
0240 {
0241     int rc = 0;
0242     char *name;
0243     struct device_node *syscon_np = NULL;
0244
0245     name = "syscon-cpu";
0246
0247     syscon_np = of_parse_phandle(np, name, 0);
0248     if (!syscon_np) {
0249         pr_err("can't find phandle %s\n", name);
0250         rc = -EINVAL;
0251         goto cleanup;
0252     }
0253
0254     cpubiuctrl_block = of_iomap(syscon_np, 0);
0255     if (!cpubiuctrl_block) {
0256         pr_err("iomap failed for cpubiuctrl_block\n");
0257         rc = -EINVAL;
0258         goto cleanup;
0259     }
0260
0261     rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
0262                     &cpu0_pwr_zone_ctrl_reg);
0263     if (rc) {
0264         pr_err("failed to read 1st entry from %s property (%d)\n", name,
0265             rc);
0266         rc = -EINVAL;
0267         goto cleanup;
0268     }
0269
0270     rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
0271                     &cpu_rst_cfg_reg);
0272     if (rc) {
0273         pr_err("failed to read 2nd entry from %s property (%d)\n", name,
0274             rc);
0275         rc = -EINVAL;
0276         goto cleanup;
0277     }
0278
0279 cleanup:
0280     of_node_put(syscon_np);
0281     return rc;
0282 }
0283
0284 static int __init setup_hifcont_regs(struct device_node *np)
0285 {
0286     int rc = 0;
0287     char *name;
0288     struct device_node *syscon_np = NULL;
0289
0290     name = "syscon-cont";
0291
0292     syscon_np = of_parse_phandle(np, name, 0);
0293     if (!syscon_np) {
0294         pr_err("can't find phandle %s\n", name);
0295         rc = -EINVAL;
0296         goto cleanup;
0297     }
0298
0299     hif_cont_block = of_iomap(syscon_np, 0);
0300     if (!hif_cont_block) {
0301         pr_err("iomap failed for hif_cont_block\n");
0302         rc = -EINVAL;
0303         goto cleanup;
0304     }
0305
0306     /* Offset is at top of hif_cont_block */
0307     hif_cont_reg = 0;
0308
0309 cleanup:
0310     of_node_put(syscon_np);
0311     return rc;
0312 }
0313
0314 static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
0315 {
0316     int rc;
0317     struct device_node *np;
0318     char *name;
0319
0320     name = "brcm,brcmstb-smpboot";
0321     np = of_find_compatible_node(NULL, NULL, name);
0322     if (!np) {
0323         pr_err("can't find compatible node %s\n", name);
0324         return;
0325     }
0326
0327     rc = setup_hifcpubiuctrl_regs(np);
0328     if (rc)
0329         goto out_put_node;
0330
0331     rc = setup_hifcont_regs(np);
0332     if (rc)
0333         goto out_put_node;
0334
0335 out_put_node:
0336     of_node_put(np);
0337 }
0338
0339 static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
0340 {
0341     /* Missing the brcm,brcmstb-smpboot DT node? */
0342     if (!cpubiuctrl_block || !hif_cont_block)
0343         return -ENODEV;
0344
0345     /* Bring up power to the core if necessary */
0346     if (brcmstb_cpu_get_power_state(cpu) == 0)
0347         brcmstb_cpu_power_on(cpu);
0348
0349     brcmstb_cpu_boot(cpu);
0350
0351     return 0;
0352 }
0353
0354 static const struct smp_operations brcmstb_smp_ops __initconst = {
0355     .smp_prepare_cpus   = brcmstb_cpu_ctrl_setup,
0356     .smp_boot_secondary = brcmstb_boot_secondary,
0357 #ifdef CONFIG_HOTPLUG_CPU
0358     .cpu_kill       = brcmstb_cpu_kill,
0359     .cpu_die        = brcmstb_cpu_die,
0360 #endif
0361 };
0362
0363 CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);