arm/mach-axxia/platsmp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-axxia/platsmp.c
0004  *
0005  * Copyright (C) 2012 LSI Corporation
0006  */
0007
0008 #include <linux/init.h>
0009 #include <linux/io.h>
0010 #include <linux/smp.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <asm/cacheflush.h>
0014
0015 /* Syscon register offsets for releasing cores from reset */
0016 #define SC_CRIT_WRITE_KEY   0x1000
0017 #define SC_RST_CPU_HOLD     0x1010
0018
0019 /*
0020  * Write the kernel entry point for secondary CPUs to the specified address
0021  */
0022 static void write_release_addr(u32 release_phys)
0023 {
0024     u32 *virt = (u32 *) phys_to_virt(release_phys);
0025     writel_relaxed(__pa_symbol(secondary_startup), virt);
0026     /* Make sure this store is visible to other CPUs */
0027     smp_wmb();
0028     __cpuc_flush_dcache_area(virt, sizeof(u32));
0029 }
0030
0031 static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
0032 {
0033     struct device_node *syscon_np;
0034     void __iomem *syscon;
0035     u32 tmp;
0036
0037     syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon");
0038     if (!syscon_np)
0039         return -ENOENT;
0040
0041     syscon = of_iomap(syscon_np, 0);
0042     of_node_put(syscon_np);
0043     if (!syscon)
0044         return -ENOMEM;
0045
0046     tmp = readl(syscon + SC_RST_CPU_HOLD);
0047     writel(0xab, syscon + SC_CRIT_WRITE_KEY);
0048     tmp &= ~(1 << cpu);
0049     writel(tmp, syscon + SC_RST_CPU_HOLD);
0050
0051     return 0;
0052 }
0053
0054 static void __init axxia_smp_prepare_cpus(unsigned int max_cpus)
0055 {
0056     int cpu_count = 0;
0057     int cpu;
0058
0059     /*
0060      * Initialise the present map, which describes the set of CPUs actually
0061      * populated at the present time.
0062      */
0063     for_each_possible_cpu(cpu) {
0064         struct device_node *np;
0065         u32 release_phys;
0066
0067         np = of_get_cpu_node(cpu, NULL);
0068         if (!np)
0069             continue;
0070         if (of_property_read_u32(np, "cpu-release-addr", &release_phys))
0071             continue;
0072
0073         if (cpu_count < max_cpus) {
0074             set_cpu_present(cpu, true);
0075             cpu_count++;
0076         }
0077
0078         if (release_phys != 0)
0079             write_release_addr(release_phys);
0080     }
0081 }
0082
0083 static const struct smp_operations axxia_smp_ops __initconst = {
0084     .smp_prepare_cpus   = axxia_smp_prepare_cpus,
0085     .smp_boot_secondary = axxia_boot_secondary,
0086 };
0087 CPU_METHOD_OF_DECLARE(axxia_smp, "lsi,syscon-release", &axxia_smp_ops);