Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * arch/arm/mach-at91/pm.c
0004  * AT91 Power Management
0005  *
0006  * Copyright (C) 2005 David Brownell
0007  */
0008 
0009 #include <linux/genalloc.h>
0010 #include <linux/io.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of.h>
0013 #include <linux/of_fdt.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/parser.h>
0016 #include <linux/suspend.h>
0017 
0018 #include <linux/clk.h>
0019 #include <linux/clk/at91_pmc.h>
0020 #include <linux/platform_data/atmel.h>
0021 
0022 #include <soc/at91/pm.h>
0023 
0024 #include <asm/cacheflush.h>
0025 #include <asm/fncpy.h>
0026 #include <asm/system_misc.h>
0027 #include <asm/suspend.h>
0028 
0029 #include "generic.h"
0030 #include "pm.h"
0031 #include "sam_secure.h"
0032 
0033 #define BACKUP_DDR_PHY_CALIBRATION  (9)
0034 
0035 /**
0036  * struct at91_pm_bu - AT91 power management backup unit data structure
0037  * @suspended: true if suspended to backup mode
0038  * @reserved: reserved
0039  * @canary: canary data for memory checking after exit from backup mode
0040  * @resume: resume API
0041  * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
0042  * of the memory
0043  */
0044 struct at91_pm_bu {
0045     int suspended;
0046     unsigned long reserved;
0047     phys_addr_t canary;
0048     phys_addr_t resume;
0049     unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
0050 };
0051 
0052 /**
0053  * struct at91_pm_sfrbu_regs - registers mapping for SFRBU
0054  * @pswbu: power switch BU control registers
0055  */
0056 struct at91_pm_sfrbu_regs {
0057     struct {
0058         u32 key;
0059         u32 ctrl;
0060         u32 state;
0061         u32 softsw;
0062     } pswbu;
0063 };
0064 
0065 /**
0066  * enum at91_pm_eth_clk - Ethernet clock indexes
0067  * @AT91_PM_ETH_PCLK: pclk index
0068  * @AT91_PM_ETH_HCLK: hclk index
0069  * @AT91_PM_ETH_MAX_CLK: max index
0070  */
0071 enum at91_pm_eth_clk {
0072     AT91_PM_ETH_PCLK,
0073     AT91_PM_ETH_HCLK,
0074     AT91_PM_ETH_MAX_CLK,
0075 };
0076 
0077 /**
0078  * enum at91_pm_eth - Ethernet controller indexes
0079  * @AT91_PM_G_ETH: gigabit Ethernet controller index
0080  * @AT91_PM_E_ETH: megabit Ethernet controller index
0081  * @AT91_PM_MAX_ETH: max index
0082  */
0083 enum at91_pm_eth {
0084     AT91_PM_G_ETH,
0085     AT91_PM_E_ETH,
0086     AT91_PM_MAX_ETH,
0087 };
0088 
0089 /**
0090  * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks
0091  * @dev: Ethernet device
0092  * @np: Ethernet device node
0093  * @clks: Ethernet clocks
0094  * @modes: power management mode that this quirk applies to
0095  * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured
0096  *         as wakeup source but buggy and no other wakeup source is
0097  *         available
0098  */
0099 struct at91_pm_quirk_eth {
0100     struct device *dev;
0101     struct device_node *np;
0102     struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK];
0103     u32 modes;
0104     u32 dns_modes;
0105 };
0106 
0107 /**
0108  * struct at91_pm_quirks - AT91 PM quirks
0109  * @eth: Ethernet quirks
0110  */
0111 struct at91_pm_quirks {
0112     struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH];
0113 };
0114 
0115 /**
0116  * struct at91_soc_pm - AT91 SoC power management data structure
0117  * @config_shdwc_ws: wakeup sources configuration function for SHDWC
0118  * @config_pmc_ws: wakeup srouces configuration function for PMC
0119  * @ws_ids: wakup sources of_device_id array
0120  * @bu: backup unit mapped data (for backup mode)
0121  * @quirks: PM quirks
0122  * @data: PM data to be used on last phase of suspend
0123  * @sfrbu_regs: SFRBU registers mapping
0124  * @memcs: memory chip select
0125  */
0126 struct at91_soc_pm {
0127     int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
0128     int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
0129     const struct of_device_id *ws_ids;
0130     struct at91_pm_bu *bu;
0131     struct at91_pm_quirks quirks;
0132     struct at91_pm_data data;
0133     struct at91_pm_sfrbu_regs sfrbu_regs;
0134     void *memcs;
0135 };
0136 
0137 /**
0138  * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes
0139  * @AT91_PM_IOMAP_SHDWC:    SHDWC controller
0140  * @AT91_PM_IOMAP_SFRBU:    SFRBU controller
0141  * @AT91_PM_IOMAP_ETHC:     Ethernet controller
0142  */
0143 enum at91_pm_iomaps {
0144     AT91_PM_IOMAP_SHDWC,
0145     AT91_PM_IOMAP_SFRBU,
0146     AT91_PM_IOMAP_ETHC,
0147 };
0148 
0149 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
0150 
0151 static struct at91_soc_pm soc_pm = {
0152     .data = {
0153         .standby_mode = AT91_PM_STANDBY,
0154         .suspend_mode = AT91_PM_ULP0,
0155     },
0156 };
0157 
0158 static const match_table_t pm_modes __initconst = {
0159     { AT91_PM_STANDBY,  "standby" },
0160     { AT91_PM_ULP0,     "ulp0" },
0161     { AT91_PM_ULP0_FAST,    "ulp0-fast" },
0162     { AT91_PM_ULP1,     "ulp1" },
0163     { AT91_PM_BACKUP,   "backup" },
0164     { -1, NULL },
0165 };
0166 
0167 #define at91_ramc_read(id, field) \
0168     __raw_readl(soc_pm.data.ramc[id] + field)
0169 
0170 #define at91_ramc_write(id, field, value) \
0171     __raw_writel(value, soc_pm.data.ramc[id] + field)
0172 
0173 static int at91_pm_valid_state(suspend_state_t state)
0174 {
0175     switch (state) {
0176         case PM_SUSPEND_ON:
0177         case PM_SUSPEND_STANDBY:
0178         case PM_SUSPEND_MEM:
0179             return 1;
0180 
0181         default:
0182             return 0;
0183     }
0184 }
0185 
0186 static int canary = 0xA5A5A5A5;
0187 
0188 struct wakeup_source_info {
0189     unsigned int pmc_fsmr_bit;
0190     unsigned int shdwc_mr_bit;
0191     bool set_polarity;
0192 };
0193 
0194 static const struct wakeup_source_info ws_info[] = {
0195     { .pmc_fsmr_bit = AT91_PMC_FSTT(10),    .set_polarity = true },
0196     { .pmc_fsmr_bit = AT91_PMC_RTCAL,   .shdwc_mr_bit = BIT(17) },
0197     { .pmc_fsmr_bit = AT91_PMC_USBAL },
0198     { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
0199     { .pmc_fsmr_bit = AT91_PMC_RTTAL },
0200     { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
0201 };
0202 
0203 static const struct of_device_id sama5d2_ws_ids[] = {
0204     { .compatible = "atmel,sama5d2-gem",        .data = &ws_info[0] },
0205     { .compatible = "atmel,sama5d2-rtc",        .data = &ws_info[1] },
0206     { .compatible = "atmel,sama5d3-udc",        .data = &ws_info[2] },
0207     { .compatible = "atmel,at91rm9200-ohci",    .data = &ws_info[2] },
0208     { .compatible = "usb-ohci",         .data = &ws_info[2] },
0209     { .compatible = "atmel,at91sam9g45-ehci",   .data = &ws_info[2] },
0210     { .compatible = "usb-ehci",         .data = &ws_info[2] },
0211     { .compatible = "atmel,sama5d2-sdhci",      .data = &ws_info[3] },
0212     { /* sentinel */ }
0213 };
0214 
0215 static const struct of_device_id sam9x60_ws_ids[] = {
0216     { .compatible = "microchip,sam9x60-rtc",    .data = &ws_info[1] },
0217     { .compatible = "atmel,at91rm9200-ohci",    .data = &ws_info[2] },
0218     { .compatible = "usb-ohci",         .data = &ws_info[2] },
0219     { .compatible = "atmel,at91sam9g45-ehci",   .data = &ws_info[2] },
0220     { .compatible = "usb-ehci",         .data = &ws_info[2] },
0221     { .compatible = "microchip,sam9x60-rtt",    .data = &ws_info[4] },
0222     { .compatible = "cdns,sam9x60-macb",        .data = &ws_info[5] },
0223     { /* sentinel */ }
0224 };
0225 
0226 static const struct of_device_id sama7g5_ws_ids[] = {
0227     { .compatible = "microchip,sama7g5-rtc",    .data = &ws_info[1] },
0228     { .compatible = "microchip,sama7g5-ohci",   .data = &ws_info[2] },
0229     { .compatible = "usb-ohci",         .data = &ws_info[2] },
0230     { .compatible = "atmel,at91sam9g45-ehci",   .data = &ws_info[2] },
0231     { .compatible = "usb-ehci",         .data = &ws_info[2] },
0232     { .compatible = "microchip,sama7g5-sdhci",  .data = &ws_info[3] },
0233     { .compatible = "microchip,sama7g5-rtt",    .data = &ws_info[4] },
0234     { /* sentinel */ }
0235 };
0236 
0237 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
0238 {
0239     const struct wakeup_source_info *wsi;
0240     const struct of_device_id *match;
0241     struct platform_device *pdev;
0242     struct device_node *np;
0243     unsigned int mode = 0, polarity = 0, val = 0;
0244 
0245     if (pm_mode != AT91_PM_ULP1)
0246         return 0;
0247 
0248     if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
0249         return -EPERM;
0250 
0251     if (!set) {
0252         writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
0253         return 0;
0254     }
0255 
0256     if (soc_pm.config_shdwc_ws)
0257         soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
0258 
0259     /* SHDWC.MR */
0260     val = readl(soc_pm.data.shdwc + 0x04);
0261 
0262     /* Loop through defined wakeup sources. */
0263     for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
0264         pdev = of_find_device_by_node(np);
0265         if (!pdev)
0266             continue;
0267 
0268         if (device_may_wakeup(&pdev->dev)) {
0269             wsi = match->data;
0270 
0271             /* Check if enabled on SHDWC. */
0272             if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
0273                 goto put_device;
0274 
0275             mode |= wsi->pmc_fsmr_bit;
0276             if (wsi->set_polarity)
0277                 polarity |= wsi->pmc_fsmr_bit;
0278         }
0279 
0280 put_device:
0281         put_device(&pdev->dev);
0282     }
0283 
0284     if (mode) {
0285         if (soc_pm.config_pmc_ws)
0286             soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
0287     } else {
0288         pr_err("AT91: PM: no ULP1 wakeup sources found!");
0289     }
0290 
0291     return mode ? 0 : -EPERM;
0292 }
0293 
0294 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
0295                     u32 *polarity)
0296 {
0297     u32 val;
0298 
0299     /* SHDWC.WUIR */
0300     val = readl(shdwc + 0x0c);
0301     *mode |= (val & 0x3ff);
0302     *polarity |= ((val >> 16) & 0x3ff);
0303 
0304     return 0;
0305 }
0306 
0307 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
0308 {
0309     writel(mode, pmc + AT91_PMC_FSMR);
0310     writel(polarity, pmc + AT91_PMC_FSPR);
0311 
0312     return 0;
0313 }
0314 
0315 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
0316 {
0317     writel(mode, pmc + AT91_PMC_FSMR);
0318 
0319     return 0;
0320 }
0321 
0322 static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth)
0323 {
0324     struct platform_device *pdev;
0325 
0326     /* Interface NA in DT. */
0327     if (!eth->np)
0328         return false;
0329 
0330     /* No quirks for this interface and current suspend mode. */
0331     if (!(eth->modes & BIT(soc_pm.data.mode)))
0332         return false;
0333 
0334     if (!eth->dev) {
0335         /* Driver not probed. */
0336         pdev = of_find_device_by_node(eth->np);
0337         if (!pdev)
0338             return false;
0339         eth->dev = &pdev->dev;
0340     }
0341 
0342     /* No quirks if device isn't a wakeup source. */
0343     if (!device_may_wakeup(eth->dev)) {
0344         put_device(eth->dev);
0345         return false;
0346     }
0347 
0348     /* put_device(eth->dev) is called at the end of suspend. */
0349     return true;
0350 }
0351 
0352 static int at91_pm_config_quirks(bool suspend)
0353 {
0354     struct at91_pm_quirk_eth *eth;
0355     int i, j, ret, tmp;
0356 
0357     /*
0358      * Ethernet IPs who's device_node pointers are stored into
0359      * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1
0360      * or both due to a hardware bug. If they receive WoL packets while in
0361      * ULP0 or ULP1 IPs could stop working or the whole system could stop
0362      * working. We cannot handle this scenario in the ethernet driver itself
0363      * as the driver is common to multiple vendors and also we only know
0364      * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle
0365      * these scenarios here, as quirks.
0366      */
0367     for (i = 0; i < AT91_PM_MAX_ETH; i++) {
0368         eth = &soc_pm.quirks.eth[i];
0369 
0370         if (!at91_pm_eth_quirk_is_valid(eth))
0371             continue;
0372 
0373         /*
0374          * For modes in dns_modes mask the system blocks if quirk is not
0375          * applied but if applied the interface doesn't act at WoL
0376          * events. Thus take care to avoid suspending if this interface
0377          * is the only configured wakeup source.
0378          */
0379         if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) {
0380             int ws_count = 0;
0381 #ifdef CONFIG_PM_SLEEP
0382             struct wakeup_source *ws;
0383 
0384             for_each_wakeup_source(ws) {
0385                 if (ws->dev == eth->dev)
0386                     continue;
0387 
0388                 ws_count++;
0389                 break;
0390             }
0391 #endif
0392 
0393             /*
0394              * Checking !ws is good for all platforms with issues
0395              * even when both G_ETH and E_ETH are available as dns_modes
0396              * is populated only on G_ETH interface.
0397              */
0398             if (!ws_count) {
0399                 pr_err("AT91: PM: Ethernet cannot resume from WoL!");
0400                 ret = -EPERM;
0401                 put_device(eth->dev);
0402                 eth->dev = NULL;
0403                 /* No need to revert clock settings for this eth. */
0404                 i--;
0405                 goto clk_unconfigure;
0406             }
0407         }
0408 
0409         if (suspend) {
0410             clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks);
0411         } else {
0412             ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK,
0413                               eth->clks);
0414             if (ret)
0415                 goto clk_unconfigure;
0416             /*
0417              * Release the reference to eth->dev taken in
0418              * at91_pm_eth_quirk_is_valid().
0419              */
0420             put_device(eth->dev);
0421             eth->dev = NULL;
0422         }
0423     }
0424 
0425     return 0;
0426 
0427 clk_unconfigure:
0428     /*
0429      * In case of resume we reach this point if clk_prepare_enable() failed.
0430      * we don't want to revert the previous clk_prepare_enable() for the
0431      * other IP.
0432      */
0433     for (j = i; j >= 0; j--) {
0434         eth = &soc_pm.quirks.eth[j];
0435         if (suspend) {
0436             if (!at91_pm_eth_quirk_is_valid(eth))
0437                 continue;
0438 
0439             tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks);
0440             if (tmp) {
0441                 pr_err("AT91: PM: failed to enable %s clocks\n",
0442                        j == AT91_PM_G_ETH ? "geth" : "eth");
0443             }
0444         } else {
0445             /*
0446              * Release the reference to eth->dev taken in
0447              * at91_pm_eth_quirk_is_valid().
0448              */
0449             put_device(eth->dev);
0450             eth->dev = NULL;
0451         }
0452     }
0453 
0454     return ret;
0455 }
0456 
0457 /*
0458  * Called after processes are frozen, but before we shutdown devices.
0459  */
0460 static int at91_pm_begin(suspend_state_t state)
0461 {
0462     int ret;
0463 
0464     switch (state) {
0465     case PM_SUSPEND_MEM:
0466         soc_pm.data.mode = soc_pm.data.suspend_mode;
0467         break;
0468 
0469     case PM_SUSPEND_STANDBY:
0470         soc_pm.data.mode = soc_pm.data.standby_mode;
0471         break;
0472 
0473     default:
0474         soc_pm.data.mode = -1;
0475     }
0476 
0477     ret = at91_pm_config_ws(soc_pm.data.mode, true);
0478     if (ret)
0479         return ret;
0480 
0481     if (soc_pm.data.mode == AT91_PM_BACKUP)
0482         soc_pm.bu->suspended = 1;
0483     else if (soc_pm.bu)
0484         soc_pm.bu->suspended = 0;
0485 
0486     return 0;
0487 }
0488 
0489 /*
0490  * Verify that all the clocks are correct before entering
0491  * slow-clock mode.
0492  */
0493 static int at91_pm_verify_clocks(void)
0494 {
0495     unsigned long scsr;
0496     int i;
0497 
0498     scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
0499 
0500     /* USB must not be using PLLB */
0501     if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
0502         pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
0503         return 0;
0504     }
0505 
0506     /* PCK0..PCK3 must be disabled, or configured to use clk32k */
0507     for (i = 0; i < 4; i++) {
0508         u32 css;
0509 
0510         if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
0511             continue;
0512         css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
0513         if (css != AT91_PMC_CSS_SLOW) {
0514             pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
0515             return 0;
0516         }
0517     }
0518 
0519     return 1;
0520 }
0521 
0522 /*
0523  * Call this from platform driver suspend() to see how deeply to suspend.
0524  * For example, some controllers (like OHCI) need one of the PLL clocks
0525  * in order to act as a wakeup source, and those are not available when
0526  * going into slow clock mode.
0527  *
0528  * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
0529  * the very same problem (but not using at91 main_clk), and it'd be better
0530  * to add one generic API rather than lots of platform-specific ones.
0531  */
0532 int at91_suspend_entering_slow_clock(void)
0533 {
0534     return (soc_pm.data.mode >= AT91_PM_ULP0);
0535 }
0536 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
0537 
0538 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
0539 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
0540 extern u32 at91_pm_suspend_in_sram_sz;
0541 
0542 static int at91_suspend_finish(unsigned long val)
0543 {
0544     unsigned char modified_gray_code[] = {
0545         0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
0546         0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
0547         0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
0548         0x10, 0x11,
0549     };
0550     unsigned int tmp, index;
0551     int i;
0552 
0553     if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
0554         /*
0555          * Bootloader will perform DDR recalibration and will try to
0556          * restore the ZQ0SR0 with the value saved here. But the
0557          * calibration is buggy and restoring some values from ZQ0SR0
0558          * is forbidden and risky thus we need to provide processed
0559          * values for these (modified gray code values).
0560          */
0561         tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
0562 
0563         /* Store pull-down output impedance select. */
0564         index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
0565         soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
0566 
0567         /* Store pull-up output impedance select. */
0568         index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
0569         soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
0570 
0571         /* Store pull-down on-die termination impedance select. */
0572         index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
0573         soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
0574 
0575         /* Store pull-up on-die termination impedance select. */
0576         index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
0577         soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
0578 
0579         /*
0580          * The 1st 8 words of memory might get corrupted in the process
0581          * of DDR PHY recalibration; it is saved here in securam and it
0582          * will be restored later, after recalibration, by bootloader
0583          */
0584         for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
0585             soc_pm.bu->ddr_phy_calibration[i] =
0586                 *((unsigned int *)soc_pm.memcs + (i - 1));
0587     }
0588 
0589     flush_cache_all();
0590     outer_disable();
0591 
0592     at91_suspend_sram_fn(&soc_pm.data);
0593 
0594     return 0;
0595 }
0596 
0597 static void at91_pm_switch_ba_to_vbat(void)
0598 {
0599     unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
0600     unsigned int val;
0601 
0602     /* Just for safety. */
0603     if (!soc_pm.data.sfrbu)
0604         return;
0605 
0606     val = readl(soc_pm.data.sfrbu + offset);
0607 
0608     /* Already on VBAT. */
0609     if (!(val & soc_pm.sfrbu_regs.pswbu.state))
0610         return;
0611 
0612     val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
0613     val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
0614     writel(val, soc_pm.data.sfrbu + offset);
0615 
0616     /* Wait for update. */
0617     val = readl(soc_pm.data.sfrbu + offset);
0618     while (val & soc_pm.sfrbu_regs.pswbu.state)
0619         val = readl(soc_pm.data.sfrbu + offset);
0620 }
0621 
0622 static void at91_pm_suspend(suspend_state_t state)
0623 {
0624     if (soc_pm.data.mode == AT91_PM_BACKUP) {
0625         at91_pm_switch_ba_to_vbat();
0626 
0627         cpu_suspend(0, at91_suspend_finish);
0628 
0629         /* The SRAM is lost between suspend cycles */
0630         at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
0631                          &at91_pm_suspend_in_sram,
0632                          at91_pm_suspend_in_sram_sz);
0633     } else {
0634         at91_suspend_finish(0);
0635     }
0636 
0637     outer_resume();
0638 }
0639 
0640 /*
0641  * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
0642  * event sources; and reduces DRAM power.  But otherwise it's identical to
0643  * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
0644  *
0645  * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
0646  * suspend more deeply, the master clock switches to the clk32k and turns off
0647  * the main oscillator
0648  *
0649  * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
0650  */
0651 static int at91_pm_enter(suspend_state_t state)
0652 {
0653     int ret;
0654 
0655     ret = at91_pm_config_quirks(true);
0656     if (ret)
0657         return ret;
0658 
0659 #ifdef CONFIG_PINCTRL_AT91
0660     /*
0661      * FIXME: this is needed to communicate between the pinctrl driver and
0662      * the PM implementation in the machine. Possibly part of the PM
0663      * implementation should be moved down into the pinctrl driver and get
0664      * called as part of the generic suspend/resume path.
0665      */
0666     at91_pinctrl_gpio_suspend();
0667 #endif
0668 
0669     switch (state) {
0670     case PM_SUSPEND_MEM:
0671     case PM_SUSPEND_STANDBY:
0672         /*
0673          * Ensure that clocks are in a valid state.
0674          */
0675         if (soc_pm.data.mode >= AT91_PM_ULP0 &&
0676             !at91_pm_verify_clocks())
0677             goto error;
0678 
0679         at91_pm_suspend(state);
0680 
0681         break;
0682 
0683     case PM_SUSPEND_ON:
0684         cpu_do_idle();
0685         break;
0686 
0687     default:
0688         pr_debug("AT91: PM - bogus suspend state %d\n", state);
0689         goto error;
0690     }
0691 
0692 error:
0693 #ifdef CONFIG_PINCTRL_AT91
0694     at91_pinctrl_gpio_resume();
0695 #endif
0696     at91_pm_config_quirks(false);
0697     return 0;
0698 }
0699 
0700 /*
0701  * Called right prior to thawing processes.
0702  */
0703 static void at91_pm_end(void)
0704 {
0705     at91_pm_config_ws(soc_pm.data.mode, false);
0706 }
0707 
0708 
0709 static const struct platform_suspend_ops at91_pm_ops = {
0710     .valid  = at91_pm_valid_state,
0711     .begin  = at91_pm_begin,
0712     .enter  = at91_pm_enter,
0713     .end    = at91_pm_end,
0714 };
0715 
0716 static struct platform_device at91_cpuidle_device = {
0717     .name = "cpuidle-at91",
0718 };
0719 
0720 /*
0721  * The AT91RM9200 goes into self-refresh mode with this command, and will
0722  * terminate self-refresh automatically on the next SDRAM access.
0723  *
0724  * Self-refresh mode is exited as soon as a memory access is made, but we don't
0725  * know for sure when that happens. However, we need to restore the low-power
0726  * mode if it was enabled before going idle. Restoring low-power mode while
0727  * still in self-refresh is "not recommended", but seems to work.
0728  */
0729 static void at91rm9200_standby(void)
0730 {
0731     asm volatile(
0732         "b    1f\n\t"
0733         ".align    5\n\t"
0734         "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
0735         "    str    %2, [%1, %3]\n\t"
0736         "    mcr    p15, 0, %0, c7, c0, 4\n\t"
0737         :
0738         : "r" (0), "r" (soc_pm.data.ramc[0]),
0739           "r" (1), "r" (AT91_MC_SDRAMC_SRR));
0740 }
0741 
0742 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
0743  * remember.
0744  */
0745 static void at91_ddr_standby(void)
0746 {
0747     /* Those two values allow us to delay self-refresh activation
0748      * to the maximum. */
0749     u32 lpr0, lpr1 = 0;
0750     u32 mdr, saved_mdr0, saved_mdr1 = 0;
0751     u32 saved_lpr0, saved_lpr1 = 0;
0752 
0753     /* LPDDR1 --> force DDR2 mode during self-refresh */
0754     saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
0755     if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
0756         mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
0757         mdr |= AT91_DDRSDRC_MD_DDR2;
0758         at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
0759     }
0760 
0761     if (soc_pm.data.ramc[1]) {
0762         saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
0763         lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
0764         lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
0765         saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
0766         if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
0767             mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
0768             mdr |= AT91_DDRSDRC_MD_DDR2;
0769             at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
0770         }
0771     }
0772 
0773     saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
0774     lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
0775     lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
0776 
0777     /* self-refresh mode now */
0778     at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
0779     if (soc_pm.data.ramc[1])
0780         at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
0781 
0782     cpu_do_idle();
0783 
0784     at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
0785     at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
0786     if (soc_pm.data.ramc[1]) {
0787         at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
0788         at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
0789     }
0790 }
0791 
0792 static void sama5d3_ddr_standby(void)
0793 {
0794     u32 lpr0;
0795     u32 saved_lpr0;
0796 
0797     saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
0798     lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
0799     lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
0800 
0801     at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
0802 
0803     cpu_do_idle();
0804 
0805     at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
0806 }
0807 
0808 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
0809  * remember.
0810  */
0811 static void at91sam9_sdram_standby(void)
0812 {
0813     u32 lpr0, lpr1 = 0;
0814     u32 saved_lpr0, saved_lpr1 = 0;
0815 
0816     if (soc_pm.data.ramc[1]) {
0817         saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
0818         lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
0819         lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
0820     }
0821 
0822     saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
0823     lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
0824     lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
0825 
0826     /* self-refresh mode now */
0827     at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
0828     if (soc_pm.data.ramc[1])
0829         at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
0830 
0831     cpu_do_idle();
0832 
0833     at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
0834     if (soc_pm.data.ramc[1])
0835         at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
0836 }
0837 
0838 static void sama7g5_standby(void)
0839 {
0840     int pwrtmg, ratio;
0841 
0842     pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
0843     ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
0844 
0845     /*
0846      * Place RAM into self-refresh after a maximum idle clocks. The maximum
0847      * idle clocks is configured by bootloader in
0848      * UDDRC_PWRMGT.SELFREF_TO_X32.
0849      */
0850     writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN,
0851            soc_pm.data.ramc[0] + UDDRC_PWRCTL);
0852     /* Divide CPU clock by 16. */
0853     writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
0854 
0855     cpu_do_idle();
0856 
0857     /* Restore previous configuration. */
0858     writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
0859     writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
0860 }
0861 
0862 struct ramc_info {
0863     void (*idle)(void);
0864     unsigned int memctrl;
0865 };
0866 
0867 static const struct ramc_info ramc_infos[] __initconst = {
0868     { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
0869     { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
0870     { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
0871     { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
0872     { .idle = sama7g5_standby, },
0873 };
0874 
0875 static const struct of_device_id ramc_ids[] __initconst = {
0876     { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
0877     { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
0878     { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
0879     { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
0880     { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], },
0881     { /*sentinel*/ }
0882 };
0883 
0884 static const struct of_device_id ramc_phy_ids[] __initconst = {
0885     { .compatible = "microchip,sama7g5-ddr3phy", },
0886     { /* Sentinel. */ },
0887 };
0888 
0889 static __init int at91_dt_ramc(bool phy_mandatory)
0890 {
0891     struct device_node *np;
0892     const struct of_device_id *of_id;
0893     int idx = 0;
0894     void *standby = NULL;
0895     const struct ramc_info *ramc;
0896     int ret;
0897 
0898     for_each_matching_node_and_match(np, ramc_ids, &of_id) {
0899         soc_pm.data.ramc[idx] = of_iomap(np, 0);
0900         if (!soc_pm.data.ramc[idx]) {
0901             pr_err("unable to map ramc[%d] cpu registers\n", idx);
0902             ret = -ENOMEM;
0903             of_node_put(np);
0904             goto unmap_ramc;
0905         }
0906 
0907         ramc = of_id->data;
0908         if (ramc) {
0909             if (!standby)
0910                 standby = ramc->idle;
0911             soc_pm.data.memctrl = ramc->memctrl;
0912         }
0913 
0914         idx++;
0915     }
0916 
0917     if (!idx) {
0918         pr_err("unable to find compatible ram controller node in dtb\n");
0919         ret = -ENODEV;
0920         goto unmap_ramc;
0921     }
0922 
0923     /* Lookup for DDR PHY node, if any. */
0924     for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
0925         soc_pm.data.ramc_phy = of_iomap(np, 0);
0926         if (!soc_pm.data.ramc_phy) {
0927             pr_err("unable to map ramc phy cpu registers\n");
0928             ret = -ENOMEM;
0929             of_node_put(np);
0930             goto unmap_ramc;
0931         }
0932     }
0933 
0934     if (phy_mandatory && !soc_pm.data.ramc_phy) {
0935         pr_err("DDR PHY is mandatory!\n");
0936         ret = -ENODEV;
0937         goto unmap_ramc;
0938     }
0939 
0940     if (!standby) {
0941         pr_warn("ramc no standby function available\n");
0942         return 0;
0943     }
0944 
0945     at91_cpuidle_device.dev.platform_data = standby;
0946 
0947     return 0;
0948 
0949 unmap_ramc:
0950     while (idx)
0951         iounmap(soc_pm.data.ramc[--idx]);
0952 
0953     return ret;
0954 }
0955 
0956 static void at91rm9200_idle(void)
0957 {
0958     /*
0959      * Disable the processor clock.  The processor will be automatically
0960      * re-enabled by an interrupt or by a reset.
0961      */
0962     writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
0963 }
0964 
0965 static void at91sam9_idle(void)
0966 {
0967     writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
0968     cpu_do_idle();
0969 }
0970 
0971 static void __init at91_pm_sram_init(void)
0972 {
0973     struct gen_pool *sram_pool;
0974     phys_addr_t sram_pbase;
0975     unsigned long sram_base;
0976     struct device_node *node;
0977     struct platform_device *pdev = NULL;
0978 
0979     for_each_compatible_node(node, NULL, "mmio-sram") {
0980         pdev = of_find_device_by_node(node);
0981         if (pdev) {
0982             of_node_put(node);
0983             break;
0984         }
0985     }
0986 
0987     if (!pdev) {
0988         pr_warn("%s: failed to find sram device!\n", __func__);
0989         return;
0990     }
0991 
0992     sram_pool = gen_pool_get(&pdev->dev, NULL);
0993     if (!sram_pool) {
0994         pr_warn("%s: sram pool unavailable!\n", __func__);
0995         goto out_put_device;
0996     }
0997 
0998     sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
0999     if (!sram_base) {
1000         pr_warn("%s: unable to alloc sram!\n", __func__);
1001         goto out_put_device;
1002     }
1003 
1004     sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
1005     at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
1006                     at91_pm_suspend_in_sram_sz, false);
1007     if (!at91_suspend_sram_fn) {
1008         pr_warn("SRAM: Could not map\n");
1009         goto out_put_device;
1010     }
1011 
1012     /* Copy the pm suspend handler to SRAM */
1013     at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
1014             &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
1015     return;
1016 
1017 out_put_device:
1018     put_device(&pdev->dev);
1019     return;
1020 }
1021 
1022 static bool __init at91_is_pm_mode_active(int pm_mode)
1023 {
1024     return (soc_pm.data.standby_mode == pm_mode ||
1025         soc_pm.data.suspend_mode == pm_mode);
1026 }
1027 
1028 static int __init at91_pm_backup_scan_memcs(unsigned long node,
1029                         const char *uname, int depth,
1030                         void *data)
1031 {
1032     const char *type;
1033     const __be32 *reg;
1034     int *located = data;
1035     int size;
1036 
1037     /* Memory node already located. */
1038     if (*located)
1039         return 0;
1040 
1041     type = of_get_flat_dt_prop(node, "device_type", NULL);
1042 
1043     /* We are scanning "memory" nodes only. */
1044     if (!type || strcmp(type, "memory"))
1045         return 0;
1046 
1047     reg = of_get_flat_dt_prop(node, "reg", &size);
1048     if (reg) {
1049         soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
1050         *located = 1;
1051     }
1052 
1053     return 0;
1054 }
1055 
1056 static int __init at91_pm_backup_init(void)
1057 {
1058     struct gen_pool *sram_pool;
1059     struct device_node *np;
1060     struct platform_device *pdev;
1061     int ret = -ENODEV, located = 0;
1062 
1063     if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
1064         !IS_ENABLED(CONFIG_SOC_SAMA7G5))
1065         return -EPERM;
1066 
1067     if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
1068         return 0;
1069 
1070     np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
1071     if (!np)
1072         return ret;
1073 
1074     pdev = of_find_device_by_node(np);
1075     of_node_put(np);
1076     if (!pdev) {
1077         pr_warn("%s: failed to find securam device!\n", __func__);
1078         return ret;
1079     }
1080 
1081     sram_pool = gen_pool_get(&pdev->dev, NULL);
1082     if (!sram_pool) {
1083         pr_warn("%s: securam pool unavailable!\n", __func__);
1084         goto securam_fail;
1085     }
1086 
1087     soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
1088     if (!soc_pm.bu) {
1089         pr_warn("%s: unable to alloc securam!\n", __func__);
1090         ret = -ENOMEM;
1091         goto securam_fail;
1092     }
1093 
1094     soc_pm.bu->suspended = 0;
1095     soc_pm.bu->canary = __pa_symbol(&canary);
1096     soc_pm.bu->resume = __pa_symbol(cpu_resume);
1097     if (soc_pm.data.ramc_phy) {
1098         of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
1099         if (!located)
1100             goto securam_fail;
1101     }
1102 
1103     return 0;
1104 
1105 securam_fail:
1106     put_device(&pdev->dev);
1107     return ret;
1108 }
1109 
1110 static void __init at91_pm_secure_init(void)
1111 {
1112     int suspend_mode;
1113     struct arm_smccc_res res;
1114 
1115     suspend_mode = soc_pm.data.suspend_mode;
1116 
1117     res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE,
1118                  suspend_mode, 0);
1119     if (res.a0 == 0) {
1120         pr_info("AT91: Secure PM: suspend mode set to %s\n",
1121             pm_modes[suspend_mode].pattern);
1122         return;
1123     }
1124 
1125     pr_warn("AT91: Secure PM: %s mode not supported !\n",
1126         pm_modes[suspend_mode].pattern);
1127 
1128     res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0);
1129     if (res.a0 == 0) {
1130         pr_warn("AT91: Secure PM: failed to get default mode\n");
1131         return;
1132     }
1133 
1134     pr_info("AT91: Secure PM: using default suspend mode %s\n",
1135         pm_modes[suspend_mode].pattern);
1136 
1137     soc_pm.data.suspend_mode = res.a1;
1138 }
1139 static const struct of_device_id atmel_shdwc_ids[] = {
1140     { .compatible = "atmel,sama5d2-shdwc" },
1141     { .compatible = "microchip,sam9x60-shdwc" },
1142     { .compatible = "microchip,sama7g5-shdwc" },
1143     { /* sentinel. */ }
1144 };
1145 
1146 static const struct of_device_id gmac_ids[] __initconst = {
1147     { .compatible = "atmel,sama5d3-gem" },
1148     { .compatible = "atmel,sama5d2-gem" },
1149     { .compatible = "atmel,sama5d29-gem" },
1150     { .compatible = "microchip,sama7g5-gem" },
1151     { },
1152 };
1153 
1154 static const struct of_device_id emac_ids[] __initconst = {
1155     { .compatible = "atmel,sama5d3-macb" },
1156     { .compatible = "microchip,sama7g5-emac" },
1157     { },
1158 };
1159 
1160 /*
1161  * Replaces _mode_to_replace with a supported mode that doesn't depend
1162  * on controller pointed by _map_bitmask
1163  * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91
1164  * PM mode
1165  * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on
1166  * controller represented by _map_bitmask, _mode_to_replace needs to be
1167  * updated
1168  * @_mode_to_replace: standby_mode or suspend_mode that need to be
1169  * updated
1170  * @_mode_to_check: standby_mode or suspend_mode; this is needed here
1171  * to avoid having standby_mode and suspend_mode set with the same AT91
1172  * PM mode
1173  */
1174 #define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \
1175                  _mode_to_check)                \
1176     do {                                \
1177         if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) {   \
1178             int _mode_to_use, _mode_complementary;      \
1179             /* Use ULP0 if it doesn't need _map_bitmask. */ \
1180             if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\
1181                 _mode_to_use = AT91_PM_ULP0;        \
1182                 _mode_complementary = AT91_PM_STANDBY;  \
1183             } else {                    \
1184                 _mode_to_use = AT91_PM_STANDBY;     \
1185                 _mode_complementary = AT91_PM_STANDBY;  \
1186             }                       \
1187                                     \
1188             if ((_mode_to_check) != _mode_to_use)       \
1189                 (_mode_to_replace) = _mode_to_use;  \
1190             else                        \
1191                 (_mode_to_replace) = _mode_complementary;\
1192         }                           \
1193     } while (0)
1194 
1195 /*
1196  * Replaces standby and suspend modes with default supported modes:
1197  * ULP0 and STANDBY.
1198  * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP()
1199  * flags
1200  * @_map: controller specific name; standby and suspend mode need to be
1201  * replaced in order to not depend on this controller
1202  */
1203 #define AT91_PM_REPLACE_MODES(_maps, _map)              \
1204     do {                                \
1205         AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
1206                      (soc_pm.data.standby_mode),    \
1207                      (soc_pm.data.suspend_mode));   \
1208         AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
1209                      (soc_pm.data.suspend_mode),    \
1210                      (soc_pm.data.standby_mode));   \
1211     } while (0)
1212 
1213 static int __init at91_pm_get_eth_clks(struct device_node *np,
1214                        struct clk_bulk_data *clks)
1215 {
1216     clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk");
1217     if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk))
1218         return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk);
1219 
1220     clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk");
1221     if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk))
1222         return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk);
1223 
1224     return 0;
1225 }
1226 
1227 static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks)
1228 {
1229     return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) ||
1230            IS_ERR(clks[AT91_PM_ETH_HCLK].clk);
1231 }
1232 
1233 static void __init at91_pm_modes_init(const u32 *maps, int len)
1234 {
1235     struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH];
1236     struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH];
1237     struct device_node *np;
1238     int ret;
1239 
1240     ret = at91_pm_backup_init();
1241     if (ret) {
1242         if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
1243             soc_pm.data.standby_mode = AT91_PM_ULP0;
1244         if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
1245             soc_pm.data.suspend_mode = AT91_PM_ULP0;
1246     }
1247 
1248     if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1249         maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
1250         np = of_find_matching_node(NULL, atmel_shdwc_ids);
1251         if (!np) {
1252             pr_warn("%s: failed to find shdwc!\n", __func__);
1253             AT91_PM_REPLACE_MODES(maps, SHDWC);
1254         } else {
1255             soc_pm.data.shdwc = of_iomap(np, 0);
1256             of_node_put(np);
1257         }
1258     }
1259 
1260     if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1261         maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
1262         np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
1263         if (!np) {
1264             pr_warn("%s: failed to find sfrbu!\n", __func__);
1265             AT91_PM_REPLACE_MODES(maps, SFRBU);
1266         } else {
1267             soc_pm.data.sfrbu = of_iomap(np, 0);
1268             of_node_put(np);
1269         }
1270     }
1271 
1272     if ((at91_is_pm_mode_active(AT91_PM_ULP1) ||
1273          at91_is_pm_mode_active(AT91_PM_ULP0) ||
1274          at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) &&
1275         (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) ||
1276          maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) {
1277         np = of_find_matching_node(NULL, gmac_ids);
1278         if (!np) {
1279             np = of_find_matching_node(NULL, emac_ids);
1280             if (np)
1281                 goto get_emac_clks;
1282             AT91_PM_REPLACE_MODES(maps, ETHC);
1283             goto unmap_unused_nodes;
1284         } else {
1285             gmac->np = np;
1286             at91_pm_get_eth_clks(np, gmac->clks);
1287         }
1288 
1289         np = of_find_matching_node(NULL, emac_ids);
1290         if (!np) {
1291             if (at91_pm_eth_clks_empty(gmac->clks))
1292                 AT91_PM_REPLACE_MODES(maps, ETHC);
1293         } else {
1294 get_emac_clks:
1295             emac->np = np;
1296             ret = at91_pm_get_eth_clks(np, emac->clks);
1297             if (ret && at91_pm_eth_clks_empty(gmac->clks)) {
1298                 of_node_put(gmac->np);
1299                 of_node_put(emac->np);
1300                 gmac->np = NULL;
1301                 emac->np = NULL;
1302             }
1303         }
1304     }
1305 
1306 unmap_unused_nodes:
1307     /* Unmap all unnecessary. */
1308     if (soc_pm.data.shdwc &&
1309         !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1310           maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
1311         iounmap(soc_pm.data.shdwc);
1312         soc_pm.data.shdwc = NULL;
1313     }
1314 
1315     if (soc_pm.data.sfrbu &&
1316         !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1317           maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
1318         iounmap(soc_pm.data.sfrbu);
1319         soc_pm.data.sfrbu = NULL;
1320     }
1321 
1322     return;
1323 }
1324 
1325 struct pmc_info {
1326     unsigned long uhp_udp_mask;
1327     unsigned long mckr;
1328     unsigned long version;
1329 };
1330 
1331 static const struct pmc_info pmc_infos[] __initconst = {
1332     {
1333         .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
1334         .mckr = 0x30,
1335         .version = AT91_PMC_V1,
1336     },
1337 
1338     {
1339         .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
1340         .mckr = 0x30,
1341         .version = AT91_PMC_V1,
1342     },
1343     {
1344         .uhp_udp_mask = AT91SAM926x_PMC_UHP,
1345         .mckr = 0x30,
1346         .version = AT91_PMC_V1,
1347     },
1348     {   .uhp_udp_mask = 0,
1349         .mckr = 0x30,
1350         .version = AT91_PMC_V1,
1351     },
1352     {
1353         .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
1354         .mckr = 0x28,
1355         .version = AT91_PMC_V2,
1356     },
1357     {
1358         .mckr = 0x28,
1359         .version = AT91_PMC_V2,
1360     },
1361 
1362 };
1363 
1364 static const struct of_device_id atmel_pmc_ids[] __initconst = {
1365     { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
1366     { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
1367     { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
1368     { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
1369     { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
1370     { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
1371     { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
1372     { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
1373     { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
1374     { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
1375     { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
1376     { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
1377     { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
1378     { /* sentinel */ },
1379 };
1380 
1381 static void __init at91_pm_modes_validate(const int *modes, int len)
1382 {
1383     u8 i, standby = 0, suspend = 0;
1384     int mode;
1385 
1386     for (i = 0; i < len; i++) {
1387         if (standby && suspend)
1388             break;
1389 
1390         if (modes[i] == soc_pm.data.standby_mode && !standby) {
1391             standby = 1;
1392             continue;
1393         }
1394 
1395         if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
1396             suspend = 1;
1397             continue;
1398         }
1399     }
1400 
1401     if (!standby) {
1402         if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
1403             mode = AT91_PM_ULP0;
1404         else
1405             mode = AT91_PM_STANDBY;
1406 
1407         pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1408             pm_modes[soc_pm.data.standby_mode].pattern,
1409             pm_modes[mode].pattern);
1410         soc_pm.data.standby_mode = mode;
1411     }
1412 
1413     if (!suspend) {
1414         if (soc_pm.data.standby_mode == AT91_PM_ULP0)
1415             mode = AT91_PM_STANDBY;
1416         else
1417             mode = AT91_PM_ULP0;
1418 
1419         pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1420             pm_modes[soc_pm.data.suspend_mode].pattern,
1421             pm_modes[mode].pattern);
1422         soc_pm.data.suspend_mode = mode;
1423     }
1424 }
1425 
1426 static void __init at91_pm_init(void (*pm_idle)(void))
1427 {
1428     struct device_node *pmc_np;
1429     const struct of_device_id *of_id;
1430     const struct pmc_info *pmc;
1431 
1432     if (at91_cpuidle_device.dev.platform_data)
1433         platform_device_register(&at91_cpuidle_device);
1434 
1435     pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
1436     soc_pm.data.pmc = of_iomap(pmc_np, 0);
1437     of_node_put(pmc_np);
1438     if (!soc_pm.data.pmc) {
1439         pr_err("AT91: PM not supported, PMC not found\n");
1440         return;
1441     }
1442 
1443     pmc = of_id->data;
1444     soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1445     soc_pm.data.pmc_mckr_offset = pmc->mckr;
1446     soc_pm.data.pmc_version = pmc->version;
1447 
1448     if (pm_idle)
1449         arm_pm_idle = pm_idle;
1450 
1451     at91_pm_sram_init();
1452 
1453     if (at91_suspend_sram_fn) {
1454         suspend_set_ops(&at91_pm_ops);
1455         pr_info("AT91: PM: standby: %s, suspend: %s\n",
1456             pm_modes[soc_pm.data.standby_mode].pattern,
1457             pm_modes[soc_pm.data.suspend_mode].pattern);
1458     } else {
1459         pr_info("AT91: PM not supported, due to no SRAM allocated\n");
1460     }
1461 }
1462 
1463 void __init at91rm9200_pm_init(void)
1464 {
1465     int ret;
1466 
1467     if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
1468         return;
1469 
1470     /*
1471      * Force STANDBY and ULP0 mode to avoid calling
1472      * at91_pm_modes_validate() which may increase booting time.
1473      * Platform supports anyway only STANDBY and ULP0 modes.
1474      */
1475     soc_pm.data.standby_mode = AT91_PM_STANDBY;
1476     soc_pm.data.suspend_mode = AT91_PM_ULP0;
1477 
1478     ret = at91_dt_ramc(false);
1479     if (ret)
1480         return;
1481 
1482     /*
1483      * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
1484      */
1485     at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
1486 
1487     at91_pm_init(at91rm9200_idle);
1488 }
1489 
1490 void __init sam9x60_pm_init(void)
1491 {
1492     static const int modes[] __initconst = {
1493         AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1494     };
1495     static const int iomaps[] __initconst = {
1496         [AT91_PM_ULP1]      = AT91_PM_IOMAP(SHDWC),
1497     };
1498     int ret;
1499 
1500     if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
1501         return;
1502 
1503     at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1504     at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1505     ret = at91_dt_ramc(false);
1506     if (ret)
1507         return;
1508 
1509     at91_pm_init(NULL);
1510 
1511     soc_pm.ws_ids = sam9x60_ws_ids;
1512     soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1513 }
1514 
1515 void __init at91sam9_pm_init(void)
1516 {
1517     int ret;
1518 
1519     if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
1520         return;
1521 
1522     /*
1523      * Force STANDBY and ULP0 mode to avoid calling
1524      * at91_pm_modes_validate() which may increase booting time.
1525      * Platform supports anyway only STANDBY and ULP0 modes.
1526      */
1527     soc_pm.data.standby_mode = AT91_PM_STANDBY;
1528     soc_pm.data.suspend_mode = AT91_PM_ULP0;
1529 
1530     ret = at91_dt_ramc(false);
1531     if (ret)
1532         return;
1533 
1534     at91_pm_init(at91sam9_idle);
1535 }
1536 
1537 void __init sama5_pm_init(void)
1538 {
1539     static const int modes[] __initconst = {
1540         AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
1541     };
1542     static const u32 iomaps[] __initconst = {
1543         [AT91_PM_ULP0]      = AT91_PM_IOMAP(ETHC),
1544         [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
1545     };
1546     int ret;
1547 
1548     if (!IS_ENABLED(CONFIG_SOC_SAMA5))
1549         return;
1550 
1551     at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1552     at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1553     ret = at91_dt_ramc(false);
1554     if (ret)
1555         return;
1556 
1557     at91_pm_init(NULL);
1558 
1559     /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */
1560     soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
1561                          BIT(AT91_PM_ULP0_FAST) |
1562                          BIT(AT91_PM_ULP1);
1563     /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */
1564     soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
1565                              BIT(AT91_PM_ULP0_FAST);
1566 }
1567 
1568 void __init sama5d2_pm_init(void)
1569 {
1570     static const int modes[] __initconst = {
1571         AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1572         AT91_PM_BACKUP,
1573     };
1574     static const u32 iomaps[] __initconst = {
1575         [AT91_PM_ULP0]      = AT91_PM_IOMAP(ETHC),
1576         [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
1577         [AT91_PM_ULP1]      = AT91_PM_IOMAP(SHDWC) |
1578                       AT91_PM_IOMAP(ETHC),
1579         [AT91_PM_BACKUP]    = AT91_PM_IOMAP(SHDWC) |
1580                       AT91_PM_IOMAP(SFRBU),
1581     };
1582     int ret;
1583 
1584     if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1585         return;
1586 
1587     if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) {
1588         pr_warn("AT91: Secure PM: ignoring standby mode\n");
1589         at91_pm_secure_init();
1590         return;
1591     }
1592 
1593     at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1594     at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1595     ret = at91_dt_ramc(false);
1596     if (ret)
1597         return;
1598 
1599     at91_pm_init(NULL);
1600 
1601     soc_pm.ws_ids = sama5d2_ws_ids;
1602     soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1603     soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1604 
1605     soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1606     soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1607     soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1608     soc_pm.sfrbu_regs.pswbu.state = BIT(3);
1609 
1610     /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */
1611     soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
1612                          BIT(AT91_PM_ULP0_FAST) |
1613                          BIT(AT91_PM_ULP1);
1614     /*
1615      * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup
1616      * source.
1617      */
1618     soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
1619                              BIT(AT91_PM_ULP0_FAST);
1620 }
1621 
1622 void __init sama7_pm_init(void)
1623 {
1624     static const int modes[] __initconst = {
1625         AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
1626     };
1627     static const u32 iomaps[] __initconst = {
1628         [AT91_PM_ULP0]      = AT91_PM_IOMAP(SFRBU),
1629         [AT91_PM_ULP1]      = AT91_PM_IOMAP(SFRBU) |
1630                       AT91_PM_IOMAP(SHDWC) |
1631                       AT91_PM_IOMAP(ETHC),
1632         [AT91_PM_BACKUP]    = AT91_PM_IOMAP(SFRBU) |
1633                       AT91_PM_IOMAP(SHDWC),
1634     };
1635     int ret;
1636 
1637     if (!IS_ENABLED(CONFIG_SOC_SAMA7))
1638         return;
1639 
1640     at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1641 
1642     ret = at91_dt_ramc(true);
1643     if (ret)
1644         return;
1645 
1646     at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1647     at91_pm_init(NULL);
1648 
1649     soc_pm.ws_ids = sama7g5_ws_ids;
1650     soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1651 
1652     soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1653     soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1654     soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1655     soc_pm.sfrbu_regs.pswbu.state = BIT(2);
1656 
1657     /* Quirks applies to ULP1 for both Ethernet interfaces. */
1658     soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1);
1659     soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1);
1660 }
1661 
1662 static int __init at91_pm_modes_select(char *str)
1663 {
1664     char *s;
1665     substring_t args[MAX_OPT_ARGS];
1666     int standby, suspend;
1667 
1668     if (!str)
1669         return 0;
1670 
1671     s = strsep(&str, ",");
1672     standby = match_token(s, pm_modes, args);
1673     if (standby < 0)
1674         return 0;
1675 
1676     suspend = match_token(str, pm_modes, args);
1677     if (suspend < 0)
1678         return 0;
1679 
1680     soc_pm.data.standby_mode = standby;
1681     soc_pm.data.suspend_mode = suspend;
1682 
1683     return 0;
1684 }
1685 early_param("atmel.pm_modes", at91_pm_modes_select);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!