arm/mach-actions/platsmp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Actions Semi Leopard
0004  *
0005  * This file is based on arm realview smp platform.
0006  *
0007  * Copyright 2012 Actions Semi Inc.
0008  * Author: Actions Semi, Inc.
0009  *
0010  * Copyright (c) 2017 Andreas Färber
0011  */
0012
0013 #include <linux/delay.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/smp.h>
0018 #include <linux/soc/actions/owl-sps.h>
0019 #include <asm/cacheflush.h>
0020 #include <asm/smp_plat.h>
0021 #include <asm/smp_scu.h>
0022
0023 #define OWL_CPU1_ADDR   0x50
0024 #define OWL_CPU1_FLAG   0x5c
0025
0026 #define OWL_CPUx_FLAG_BOOT  0x55aa
0027
0028 #define OWL_SPS_PG_CTL_PWR_CPU2 BIT(5)
0029 #define OWL_SPS_PG_CTL_PWR_CPU3 BIT(6)
0030 #define OWL_SPS_PG_CTL_ACK_CPU2 BIT(21)
0031 #define OWL_SPS_PG_CTL_ACK_CPU3 BIT(22)
0032
0033 static void __iomem *scu_base_addr;
0034 static void __iomem *sps_base_addr;
0035 static void __iomem *timer_base_addr;
0036 static int ncores;
0037
0038 static int s500_wakeup_secondary(unsigned int cpu)
0039 {
0040     int ret;
0041
0042     if (cpu > 3)
0043         return -EINVAL;
0044
0045     /* The generic PM domain driver is not available this early. */
0046     switch (cpu) {
0047     case 2:
0048         ret = owl_sps_set_pg(sps_base_addr,
0049                              OWL_SPS_PG_CTL_PWR_CPU2,
0050                      OWL_SPS_PG_CTL_ACK_CPU2, true);
0051         if (ret)
0052             return ret;
0053         break;
0054     case 3:
0055         ret = owl_sps_set_pg(sps_base_addr,
0056                              OWL_SPS_PG_CTL_PWR_CPU3,
0057                      OWL_SPS_PG_CTL_ACK_CPU3, true);
0058         if (ret)
0059             return ret;
0060         break;
0061     }
0062
0063     /* wait for CPUx to run to WFE instruction */
0064     udelay(200);
0065
0066     writel(__pa_symbol(secondary_startup),
0067            timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
0068     writel(OWL_CPUx_FLAG_BOOT,
0069            timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
0070
0071     dsb_sev();
0072     mb();
0073
0074     return 0;
0075 }
0076
0077 static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
0078 {
0079     int ret;
0080
0081     ret = s500_wakeup_secondary(cpu);
0082     if (ret)
0083         return ret;
0084
0085     udelay(10);
0086
0087     smp_send_reschedule(cpu);
0088
0089     writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
0090     writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
0091
0092     return 0;
0093 }
0094
0095 static void __init s500_smp_prepare_cpus(unsigned int max_cpus)
0096 {
0097     struct device_node *node;
0098
0099     node = of_find_compatible_node(NULL, NULL, "actions,s500-timer");
0100     if (!node) {
0101         pr_err("%s: missing timer\n", __func__);
0102         return;
0103     }
0104
0105     timer_base_addr = of_iomap(node, 0);
0106     if (!timer_base_addr) {
0107         pr_err("%s: could not map timer registers\n", __func__);
0108         return;
0109     }
0110
0111     node = of_find_compatible_node(NULL, NULL, "actions,s500-sps");
0112     if (!node) {
0113         pr_err("%s: missing sps\n", __func__);
0114         return;
0115     }
0116
0117     sps_base_addr = of_iomap(node, 0);
0118     if (!sps_base_addr) {
0119         pr_err("%s: could not map sps registers\n", __func__);
0120         return;
0121     }
0122
0123     if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
0124         node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
0125         if (!node) {
0126             pr_err("%s: missing scu\n", __func__);
0127             return;
0128         }
0129
0130         scu_base_addr = of_iomap(node, 0);
0131         if (!scu_base_addr) {
0132             pr_err("%s: could not map scu registers\n", __func__);
0133             return;
0134         }
0135
0136         /*
0137          * While the number of cpus is gathered from dt, also get the
0138          * number of cores from the scu to verify this value when
0139          * booting the cores.
0140          */
0141         ncores = scu_get_core_count(scu_base_addr);
0142         pr_debug("%s: ncores %d\n", __func__, ncores);
0143
0144         scu_enable(scu_base_addr);
0145     }
0146 }
0147
0148 static const struct smp_operations s500_smp_ops __initconst = {
0149     .smp_prepare_cpus = s500_smp_prepare_cpus,
0150     .smp_boot_secondary = s500_smp_boot_secondary,
0151 };
0152 CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops);