arm/kernel/smp_tlb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/kernel/smp_tlb.c
0004  *
0005  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
0006  */
0007 #include <linux/preempt.h>
0008 #include <linux/smp.h>
0009 #include <linux/uaccess.h>
0010
0011 #include <asm/smp_plat.h>
0012 #include <asm/tlbflush.h>
0013 #include <asm/mmu_context.h>
0014
0015 /**********************************************************************/
0016
0017 /*
0018  * TLB operations
0019  */
0020 struct tlb_args {
0021     struct vm_area_struct *ta_vma;
0022     unsigned long ta_start;
0023     unsigned long ta_end;
0024 };
0025
0026 static inline void ipi_flush_tlb_all(void *ignored)
0027 {
0028     local_flush_tlb_all();
0029 }
0030
0031 static inline void ipi_flush_tlb_mm(void *arg)
0032 {
0033     struct mm_struct *mm = (struct mm_struct *)arg;
0034
0035     local_flush_tlb_mm(mm);
0036 }
0037
0038 static inline void ipi_flush_tlb_page(void *arg)
0039 {
0040     struct tlb_args *ta = (struct tlb_args *)arg;
0041     unsigned int __ua_flags = uaccess_save_and_enable();
0042
0043     local_flush_tlb_page(ta->ta_vma, ta->ta_start);
0044
0045     uaccess_restore(__ua_flags);
0046 }
0047
0048 static inline void ipi_flush_tlb_kernel_page(void *arg)
0049 {
0050     struct tlb_args *ta = (struct tlb_args *)arg;
0051
0052     local_flush_tlb_kernel_page(ta->ta_start);
0053 }
0054
0055 static inline void ipi_flush_tlb_range(void *arg)
0056 {
0057     struct tlb_args *ta = (struct tlb_args *)arg;
0058     unsigned int __ua_flags = uaccess_save_and_enable();
0059
0060     local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
0061
0062     uaccess_restore(__ua_flags);
0063 }
0064
0065 static inline void ipi_flush_tlb_kernel_range(void *arg)
0066 {
0067     struct tlb_args *ta = (struct tlb_args *)arg;
0068
0069     local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
0070 }
0071
0072 static inline void ipi_flush_bp_all(void *ignored)
0073 {
0074     local_flush_bp_all();
0075 }
0076
0077 #ifdef CONFIG_ARM_ERRATA_798181
0078 bool (*erratum_a15_798181_handler)(void);
0079
0080 static bool erratum_a15_798181_partial(void)
0081 {
0082     asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
0083     dsb(ish);
0084     return false;
0085 }
0086
0087 static bool erratum_a15_798181_broadcast(void)
0088 {
0089     asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
0090     dsb(ish);
0091     return true;
0092 }
0093
0094 void erratum_a15_798181_init(void)
0095 {
0096     unsigned int midr = read_cpuid_id();
0097     unsigned int revidr = read_cpuid(CPUID_REVIDR);
0098
0099     /* Brahma-B15 r0p0..r0p2 affected
0100      * Cortex-A15 r0p0..r3p3 w/o ECO fix affected
0101      * Fixes applied to A15 with respect to the revision and revidr are:
0102      *
0103      * r0p0-r2p1: No fixes applied
0104      * r2p2,r2p3:
0105      *  REVIDR[4]: 798181 Moving a virtual page that is being accessed
0106      *         by an active process can lead to unexpected behavior
0107      *  REVIDR[9]: Not defined
0108      * r2p4,r3p0,r3p1,r3p2:
0109      *  REVIDR[4]: 798181 Moving a virtual page that is being accessed
0110      *         by an active process can lead to unexpected behavior
0111      *  REVIDR[9]: 798181 Moving a virtual page that is being accessed
0112      *         by an active process can lead to unexpected behavior
0113      *         - This is an update to a previously released ECO.
0114      * r3p3:
0115      *  REVIDR[4]: Reserved
0116      *  REVIDR[9]: 798181 Moving a virtual page that is being accessed
0117      *         by an active process can lead to unexpected behavior
0118      *         - This is an update to a previously released ECO.
0119      *
0120      * Handling:
0121      *  REVIDR[9] set -> No WA
0122      *  REVIDR[4] set, REVIDR[9] cleared -> Partial WA
0123      *  Both cleared -> Full WA
0124      */
0125     if ((midr & 0xff0ffff0) == 0x420f00f0 && midr <= 0x420f00f2) {
0126         erratum_a15_798181_handler = erratum_a15_798181_broadcast;
0127     } else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr < 0x412fc0f2) {
0128         erratum_a15_798181_handler = erratum_a15_798181_broadcast;
0129     } else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr < 0x412fc0f4) {
0130         if (revidr & 0x10)
0131             erratum_a15_798181_handler =
0132                 erratum_a15_798181_partial;
0133         else
0134             erratum_a15_798181_handler =
0135                 erratum_a15_798181_broadcast;
0136     } else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr < 0x413fc0f3) {
0137         if ((revidr & 0x210) == 0)
0138             erratum_a15_798181_handler =
0139                 erratum_a15_798181_broadcast;
0140         else if (revidr & 0x10)
0141             erratum_a15_798181_handler =
0142                 erratum_a15_798181_partial;
0143     } else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr < 0x414fc0f0) {
0144         if ((revidr & 0x200) == 0)
0145             erratum_a15_798181_handler =
0146                 erratum_a15_798181_partial;
0147     }
0148 }
0149 #endif
0150
0151 static void ipi_flush_tlb_a15_erratum(void *arg)
0152 {
0153     dmb();
0154 }
0155
0156 static void broadcast_tlb_a15_erratum(void)
0157 {
0158     if (!erratum_a15_798181())
0159         return;
0160
0161     smp_call_function(ipi_flush_tlb_a15_erratum, NULL, 1);
0162 }
0163
0164 static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
0165 {
0166     int this_cpu;
0167     cpumask_t mask = { CPU_BITS_NONE };
0168
0169     if (!erratum_a15_798181())
0170         return;
0171
0172     this_cpu = get_cpu();
0173     a15_erratum_get_cpumask(this_cpu, mm, &mask);
0174     smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
0175     put_cpu();
0176 }
0177
0178 void flush_tlb_all(void)
0179 {
0180     if (tlb_ops_need_broadcast())
0181         on_each_cpu(ipi_flush_tlb_all, NULL, 1);
0182     else
0183         __flush_tlb_all();
0184     broadcast_tlb_a15_erratum();
0185 }
0186
0187 void flush_tlb_mm(struct mm_struct *mm)
0188 {
0189     if (tlb_ops_need_broadcast())
0190         on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
0191     else
0192         __flush_tlb_mm(mm);
0193     broadcast_tlb_mm_a15_erratum(mm);
0194 }
0195
0196 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
0197 {
0198     if (tlb_ops_need_broadcast()) {
0199         struct tlb_args ta;
0200         ta.ta_vma = vma;
0201         ta.ta_start = uaddr;
0202         on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page,
0203                     &ta, 1);
0204     } else
0205         __flush_tlb_page(vma, uaddr);
0206     broadcast_tlb_mm_a15_erratum(vma->vm_mm);
0207 }
0208
0209 void flush_tlb_kernel_page(unsigned long kaddr)
0210 {
0211     if (tlb_ops_need_broadcast()) {
0212         struct tlb_args ta;
0213         ta.ta_start = kaddr;
0214         on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
0215     } else
0216         __flush_tlb_kernel_page(kaddr);
0217     broadcast_tlb_a15_erratum();
0218 }
0219
0220 void flush_tlb_range(struct vm_area_struct *vma,
0221                      unsigned long start, unsigned long end)
0222 {
0223     if (tlb_ops_need_broadcast()) {
0224         struct tlb_args ta;
0225         ta.ta_vma = vma;
0226         ta.ta_start = start;
0227         ta.ta_end = end;
0228         on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range,
0229                     &ta, 1);
0230     } else
0231         local_flush_tlb_range(vma, start, end);
0232     broadcast_tlb_mm_a15_erratum(vma->vm_mm);
0233 }
0234
0235 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
0236 {
0237     if (tlb_ops_need_broadcast()) {
0238         struct tlb_args ta;
0239         ta.ta_start = start;
0240         ta.ta_end = end;
0241         on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
0242     } else
0243         local_flush_tlb_kernel_range(start, end);
0244     broadcast_tlb_a15_erratum();
0245 }
0246
0247 void flush_bp_all(void)
0248 {
0249     if (tlb_ops_need_broadcast())
0250         on_each_cpu(ipi_flush_bp_all, NULL, 1);
0251     else
0252         __flush_bp_all();
0253 }