arm/kernel/irq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/kernel/irq.c
0004  *
0005  *  Copyright (C) 1992 Linus Torvalds
0006  *  Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
0007  *
0008  *  Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
0009  *  Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and
0010  *  Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>.
0011  *
0012  *  This file contains the code used by various IRQ handling routines:
0013  *  asking for different IRQ's should be done through these routines
0014  *  instead of just grabbing them. Thus setups with different IRQ numbers
0015  *  shouldn't result in any weird surprises, and installing new handlers
0016  *  should be easier.
0017  *
0018  *  IRQ's are in fact implemented a bit like signal handlers for the kernel.
0019  *  Naturally it's not a 1:1 relation, but there are similarities.
0020  */
0021 #include <linux/signal.h>
0022 #include <linux/ioport.h>
0023 #include <linux/interrupt.h>
0024 #include <linux/irq.h>
0025 #include <linux/irqchip.h>
0026 #include <linux/random.h>
0027 #include <linux/smp.h>
0028 #include <linux/init.h>
0029 #include <linux/seq_file.h>
0030 #include <linux/errno.h>
0031 #include <linux/list.h>
0032 #include <linux/kallsyms.h>
0033 #include <linux/proc_fs.h>
0034 #include <linux/export.h>
0035
0036 #include <asm/hardware/cache-l2x0.h>
0037 #include <asm/hardware/cache-uniphier.h>
0038 #include <asm/outercache.h>
0039 #include <asm/softirq_stack.h>
0040 #include <asm/exception.h>
0041 #include <asm/mach/arch.h>
0042 #include <asm/mach/irq.h>
0043 #include <asm/mach/time.h>
0044
0045 #include "reboot.h"
0046
0047 unsigned long irq_err_count;
0048
0049 #ifdef CONFIG_IRQSTACKS
0050
0051 asmlinkage DEFINE_PER_CPU_READ_MOSTLY(u8 *, irq_stack_ptr);
0052
0053 static void __init init_irq_stacks(void)
0054 {
0055     u8 *stack;
0056     int cpu;
0057
0058     for_each_possible_cpu(cpu) {
0059         if (!IS_ENABLED(CONFIG_VMAP_STACK))
0060             stack = (u8 *)__get_free_pages(GFP_KERNEL,
0061                                THREAD_SIZE_ORDER);
0062         else
0063             stack = __vmalloc_node(THREAD_SIZE, THREAD_ALIGN,
0064                            THREADINFO_GFP, NUMA_NO_NODE,
0065                            __builtin_return_address(0));
0066
0067         if (WARN_ON(!stack))
0068             break;
0069         per_cpu(irq_stack_ptr, cpu) = &stack[THREAD_SIZE];
0070     }
0071 }
0072
0073 #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
0074 static void ____do_softirq(void *arg)
0075 {
0076     __do_softirq();
0077 }
0078
0079 void do_softirq_own_stack(void)
0080 {
0081     call_with_stack(____do_softirq, NULL,
0082             __this_cpu_read(irq_stack_ptr));
0083 }
0084 #endif
0085 #endif
0086
0087 int arch_show_interrupts(struct seq_file *p, int prec)
0088 {
0089 #ifdef CONFIG_FIQ
0090     show_fiq_list(p, prec);
0091 #endif
0092 #ifdef CONFIG_SMP
0093     show_ipi_list(p, prec);
0094 #endif
0095     seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
0096     return 0;
0097 }
0098
0099 /*
0100  * handle_IRQ handles all hardware IRQ's.  Decoded IRQs should
0101  * not come via this function.  Instead, they should provide their
0102  * own 'handler'.  Used by platform code implementing C-based 1st
0103  * level decoding.
0104  */
0105 void handle_IRQ(unsigned int irq, struct pt_regs *regs)
0106 {
0107     struct irq_desc *desc;
0108
0109     /*
0110      * Some hardware gives randomly wrong interrupts.  Rather
0111      * than crashing, do something sensible.
0112      */
0113     if (unlikely(!irq || irq >= nr_irqs))
0114         desc = NULL;
0115     else
0116         desc = irq_to_desc(irq);
0117
0118     if (likely(desc))
0119         handle_irq_desc(desc);
0120     else
0121         ack_bad_irq(irq);
0122 }
0123
0124 void __init init_IRQ(void)
0125 {
0126     int ret;
0127
0128 #ifdef CONFIG_IRQSTACKS
0129     init_irq_stacks();
0130 #endif
0131
0132     if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
0133         irqchip_init();
0134     else
0135         machine_desc->init_irq();
0136
0137     if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
0138         (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
0139         if (!outer_cache.write_sec)
0140             outer_cache.write_sec = machine_desc->l2c_write_sec;
0141         ret = l2x0_of_init(machine_desc->l2c_aux_val,
0142                    machine_desc->l2c_aux_mask);
0143         if (ret && ret != -ENODEV)
0144             pr_err("L2C: failed to init: %d\n", ret);
0145     }
0146
0147     uniphier_cache_init();
0148 }
0149
0150 #ifdef CONFIG_SPARSE_IRQ
0151 int __init arch_probe_nr_irqs(void)
0152 {
0153     nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS;
0154     return nr_irqs;
0155 }
0156 #endif