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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  linux/arch/arm/kernel/bios32.c
0004  *
0005  *  PCI bios-type initialisation for PCI machines
0006  *
0007  *  Bits taken from various places.
0008  */
0009 #include <linux/export.h>
0010 #include <linux/kernel.h>
0011 #include <linux/pci.h>
0012 #include <linux/slab.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 
0016 #include <asm/mach-types.h>
0017 #include <asm/mach/map.h>
0018 #include <asm/mach/pci.h>
0019 
0020 static int debug_pci;
0021 
0022 /*
0023  * We can't use pci_get_device() here since we are
0024  * called from interrupt context.
0025  */
0026 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
0027 {
0028     struct pci_dev *dev;
0029 
0030     list_for_each_entry(dev, &bus->devices, bus_list) {
0031         u16 status;
0032 
0033         /*
0034          * ignore host bridge - we handle
0035          * that separately
0036          */
0037         if (dev->bus->number == 0 && dev->devfn == 0)
0038             continue;
0039 
0040         pci_read_config_word(dev, PCI_STATUS, &status);
0041         if (status == 0xffff)
0042             continue;
0043 
0044         if ((status & status_mask) == 0)
0045             continue;
0046 
0047         /* clear the status errors */
0048         pci_write_config_word(dev, PCI_STATUS, status & status_mask);
0049 
0050         if (warn)
0051             printk("(%s: %04X) ", pci_name(dev), status);
0052     }
0053 
0054     list_for_each_entry(dev, &bus->devices, bus_list)
0055         if (dev->subordinate)
0056             pcibios_bus_report_status(dev->subordinate, status_mask, warn);
0057 }
0058 
0059 void pcibios_report_status(u_int status_mask, int warn)
0060 {
0061     struct pci_bus *bus;
0062 
0063     list_for_each_entry(bus, &pci_root_buses, node)
0064         pcibios_bus_report_status(bus, status_mask, warn);
0065 }
0066 
0067 /*
0068  * We don't use this to fix the device, but initialisation of it.
0069  * It's not the correct use for this, but it works.
0070  * Note that the arbiter/ISA bridge appears to be buggy, specifically in
0071  * the following area:
0072  * 1. park on CPU
0073  * 2. ISA bridge ping-pong
0074  * 3. ISA bridge master handling of target RETRY
0075  *
0076  * Bug 3 is responsible for the sound DMA grinding to a halt.  We now
0077  * live with bug 2.
0078  */
0079 static void pci_fixup_83c553(struct pci_dev *dev)
0080 {
0081     /*
0082      * Set memory region to start at address 0, and enable IO
0083      */
0084     pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
0085     pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
0086 
0087     dev->resource[0].end -= dev->resource[0].start;
0088     dev->resource[0].start = 0;
0089 
0090     /*
0091      * All memory requests from ISA to be channelled to PCI
0092      */
0093     pci_write_config_byte(dev, 0x48, 0xff);
0094 
0095     /*
0096      * Enable ping-pong on bus master to ISA bridge transactions.
0097      * This improves the sound DMA substantially.  The fixed
0098      * priority arbiter also helps (see below).
0099      */
0100     pci_write_config_byte(dev, 0x42, 0x01);
0101 
0102     /*
0103      * Enable PCI retry
0104      */
0105     pci_write_config_byte(dev, 0x40, 0x22);
0106 
0107     /*
0108      * We used to set the arbiter to "park on last master" (bit
0109      * 1 set), but unfortunately the CyberPro does not park the
0110      * bus.  We must therefore park on CPU.  Unfortunately, this
0111      * may trigger yet another bug in the 553.
0112      */
0113     pci_write_config_byte(dev, 0x83, 0x02);
0114 
0115     /*
0116      * Make the ISA DMA request lowest priority, and disable
0117      * rotating priorities completely.
0118      */
0119     pci_write_config_byte(dev, 0x80, 0x11);
0120     pci_write_config_byte(dev, 0x81, 0x00);
0121 
0122     /*
0123      * Route INTA input to IRQ 11, and set IRQ11 to be level
0124      * sensitive.
0125      */
0126     pci_write_config_word(dev, 0x44, 0xb000);
0127     outb(0x08, 0x4d1);
0128 }
0129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
0130 
0131 static void pci_fixup_unassign(struct pci_dev *dev)
0132 {
0133     dev->resource[0].end -= dev->resource[0].start;
0134     dev->resource[0].start = 0;
0135 }
0136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
0137 
0138 /*
0139  * Prevent the PCI layer from seeing the resources allocated to this device
0140  * if it is the host bridge by marking it as such.  These resources are of
0141  * no consequence to the PCI layer (they are handled elsewhere).
0142  */
0143 static void pci_fixup_dec21285(struct pci_dev *dev)
0144 {
0145     int i;
0146 
0147     if (dev->devfn == 0) {
0148         dev->class &= 0xff;
0149         dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
0150         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
0151             dev->resource[i].start = 0;
0152             dev->resource[i].end   = 0;
0153             dev->resource[i].flags = 0;
0154         }
0155     }
0156 }
0157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
0158 
0159 /*
0160  * PCI IDE controllers use non-standard I/O port decoding, respect it.
0161  */
0162 static void pci_fixup_ide_bases(struct pci_dev *dev)
0163 {
0164     struct resource *r;
0165     int i;
0166 
0167     if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
0168         return;
0169 
0170     for (i = 0; i < PCI_NUM_RESOURCES; i++) {
0171         r = dev->resource + i;
0172         if ((r->start & ~0x80) == 0x374) {
0173             r->start |= 2;
0174             r->end = r->start;
0175         }
0176     }
0177 }
0178 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
0179 
0180 /*
0181  * Put the DEC21142 to sleep
0182  */
0183 static void pci_fixup_dec21142(struct pci_dev *dev)
0184 {
0185     pci_write_config_dword(dev, 0x40, 0x80000000);
0186 }
0187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
0188 
0189 /*
0190  * The CY82C693 needs some rather major fixups to ensure that it does
0191  * the right thing.  Idea from the Alpha people, with a few additions.
0192  *
0193  * We ensure that the IDE base registers are set to 1f0/3f4 for the
0194  * primary bus, and 170/374 for the secondary bus.  Also, hide them
0195  * from the PCI subsystem view as well so we won't try to perform
0196  * our own auto-configuration on them.
0197  *
0198  * In addition, we ensure that the PCI IDE interrupts are routed to
0199  * IRQ 14 and IRQ 15 respectively.
0200  *
0201  * The above gets us to a point where the IDE on this device is
0202  * functional.  However, The CY82C693U _does not work_ in bus
0203  * master mode without locking the PCI bus solid.
0204  */
0205 static void pci_fixup_cy82c693(struct pci_dev *dev)
0206 {
0207     if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
0208         u32 base0, base1;
0209 
0210         if (dev->class & 0x80) {    /* primary */
0211             base0 = 0x1f0;
0212             base1 = 0x3f4;
0213         } else {            /* secondary */
0214             base0 = 0x170;
0215             base1 = 0x374;
0216         }
0217 
0218         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
0219                        base0 | PCI_BASE_ADDRESS_SPACE_IO);
0220         pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
0221                        base1 | PCI_BASE_ADDRESS_SPACE_IO);
0222 
0223         dev->resource[0].start = 0;
0224         dev->resource[0].end   = 0;
0225         dev->resource[0].flags = 0;
0226 
0227         dev->resource[1].start = 0;
0228         dev->resource[1].end   = 0;
0229         dev->resource[1].flags = 0;
0230     } else if (PCI_FUNC(dev->devfn) == 0) {
0231         /*
0232          * Setup IDE IRQ routing.
0233          */
0234         pci_write_config_byte(dev, 0x4b, 14);
0235         pci_write_config_byte(dev, 0x4c, 15);
0236 
0237         /*
0238          * Disable FREQACK handshake, enable USB.
0239          */
0240         pci_write_config_byte(dev, 0x4d, 0x41);
0241 
0242         /*
0243          * Enable PCI retry, and PCI post-write buffer.
0244          */
0245         pci_write_config_byte(dev, 0x44, 0x17);
0246 
0247         /*
0248          * Enable ISA master and DMA post write buffering.
0249          */
0250         pci_write_config_byte(dev, 0x45, 0x03);
0251     }
0252 }
0253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
0254 
0255 /*
0256  * If the bus contains any of these devices, then we must not turn on
0257  * parity checking of any kind.  Currently this is CyberPro 20x0 only.
0258  */
0259 static inline int pdev_bad_for_parity(struct pci_dev *dev)
0260 {
0261     return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
0262          (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
0263           dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
0264         (dev->vendor == PCI_VENDOR_ID_ITE &&
0265          dev->device == PCI_DEVICE_ID_ITE_8152));
0266 
0267 }
0268 
0269 /*
0270  * pcibios_fixup_bus - Called after each bus is probed,
0271  * but before its children are examined.
0272  */
0273 void pcibios_fixup_bus(struct pci_bus *bus)
0274 {
0275     struct pci_dev *dev;
0276     u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
0277 
0278     /*
0279      * Walk the devices on this bus, working out what we can
0280      * and can't support.
0281      */
0282     list_for_each_entry(dev, &bus->devices, bus_list) {
0283         u16 status;
0284 
0285         pci_read_config_word(dev, PCI_STATUS, &status);
0286 
0287         /*
0288          * If any device on this bus does not support fast back
0289          * to back transfers, then the bus as a whole is not able
0290          * to support them.  Having fast back to back transfers
0291          * on saves us one PCI cycle per transaction.
0292          */
0293         if (!(status & PCI_STATUS_FAST_BACK))
0294             features &= ~PCI_COMMAND_FAST_BACK;
0295 
0296         if (pdev_bad_for_parity(dev))
0297             features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
0298 
0299         switch (dev->class >> 8) {
0300         case PCI_CLASS_BRIDGE_PCI:
0301             pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
0302             status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
0303             status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
0304             pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
0305             break;
0306 
0307         case PCI_CLASS_BRIDGE_CARDBUS:
0308             pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
0309             status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
0310             pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
0311             break;
0312         }
0313     }
0314 
0315     /*
0316      * Now walk the devices again, this time setting them up.
0317      */
0318     list_for_each_entry(dev, &bus->devices, bus_list) {
0319         u16 cmd;
0320 
0321         pci_read_config_word(dev, PCI_COMMAND, &cmd);
0322         cmd |= features;
0323         pci_write_config_word(dev, PCI_COMMAND, cmd);
0324 
0325         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
0326                       L1_CACHE_BYTES >> 2);
0327     }
0328 
0329     /*
0330      * Propagate the flags to the PCI bridge.
0331      */
0332     if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
0333         if (features & PCI_COMMAND_FAST_BACK)
0334             bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
0335         if (features & PCI_COMMAND_PARITY)
0336             bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
0337     }
0338 
0339     /*
0340      * Report what we did for this bus
0341      */
0342     pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
0343         bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
0344 }
0345 EXPORT_SYMBOL(pcibios_fixup_bus);
0346 
0347 /*
0348  * Swizzle the device pin each time we cross a bridge.  If a platform does
0349  * not provide a swizzle function, we perform the standard PCI swizzling.
0350  *
0351  * The default swizzling walks up the bus tree one level at a time, applying
0352  * the standard swizzle function at each step, stopping when it finds the PCI
0353  * root bus.  This will return the slot number of the bridge device on the
0354  * root bus and the interrupt pin on that device which should correspond
0355  * with the downstream device interrupt.
0356  *
0357  * Platforms may override this, in which case the slot and pin returned
0358  * depend entirely on the platform code.  However, please note that the
0359  * PCI standard swizzle is implemented on plug-in cards and Cardbus based
0360  * PCI extenders, so it can not be ignored.
0361  */
0362 static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
0363 {
0364     struct pci_sys_data *sys = dev->sysdata;
0365     int slot, oldpin = *pin;
0366 
0367     if (sys->swizzle)
0368         slot = sys->swizzle(dev, pin);
0369     else
0370         slot = pci_common_swizzle(dev, pin);
0371 
0372     if (debug_pci)
0373         printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
0374             pci_name(dev), oldpin, *pin, slot);
0375 
0376     return slot;
0377 }
0378 
0379 /*
0380  * Map a slot/pin to an IRQ.
0381  */
0382 static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0383 {
0384     struct pci_sys_data *sys = dev->sysdata;
0385     int irq = -1;
0386 
0387     if (sys->map_irq)
0388         irq = sys->map_irq(dev, slot, pin);
0389 
0390     if (debug_pci)
0391         printk("PCI: %s mapping slot %d pin %d => irq %d\n",
0392             pci_name(dev), slot, pin, irq);
0393 
0394     return irq;
0395 }
0396 
0397 static int pcibios_init_resource(int busnr, struct pci_sys_data *sys)
0398 {
0399     int ret;
0400     struct resource_entry *window;
0401 
0402     if (list_empty(&sys->resources)) {
0403         pci_add_resource_offset(&sys->resources,
0404              &iomem_resource, sys->mem_offset);
0405     }
0406 
0407     resource_list_for_each_entry(window, &sys->resources)
0408         if (resource_type(window->res) == IORESOURCE_IO)
0409             return 0;
0410 
0411     sys->io_res.start = (busnr * SZ_64K) ?  : pcibios_min_io;
0412     sys->io_res.end = (busnr + 1) * SZ_64K - 1;
0413     sys->io_res.flags = IORESOURCE_IO;
0414     sys->io_res.name = sys->io_res_name;
0415     sprintf(sys->io_res_name, "PCI%d I/O", busnr);
0416 
0417     ret = request_resource(&ioport_resource, &sys->io_res);
0418     if (ret) {
0419         pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
0420         return ret;
0421     }
0422     pci_add_resource_offset(&sys->resources, &sys->io_res,
0423                 sys->io_offset);
0424 
0425     return 0;
0426 }
0427 
0428 static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
0429                 struct list_head *head)
0430 {
0431     struct pci_sys_data *sys = NULL;
0432     int ret;
0433     int nr, busnr;
0434 
0435     for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
0436         struct pci_host_bridge *bridge;
0437 
0438         bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data));
0439         if (WARN(!bridge, "PCI: unable to allocate bridge!"))
0440             break;
0441 
0442         sys = pci_host_bridge_priv(bridge);
0443 
0444         sys->busnr   = busnr;
0445         sys->swizzle = hw->swizzle;
0446         sys->map_irq = hw->map_irq;
0447         INIT_LIST_HEAD(&sys->resources);
0448 
0449         if (hw->private_data)
0450             sys->private_data = hw->private_data[nr];
0451 
0452         ret = hw->setup(nr, sys);
0453 
0454         if (ret > 0) {
0455 
0456             ret = pcibios_init_resource(nr, sys);
0457             if (ret)  {
0458                 pci_free_host_bridge(bridge);
0459                 break;
0460             }
0461 
0462             bridge->map_irq = pcibios_map_irq;
0463             bridge->swizzle_irq = pcibios_swizzle;
0464 
0465             if (hw->scan)
0466                 ret = hw->scan(nr, bridge);
0467             else {
0468                 list_splice_init(&sys->resources,
0469                          &bridge->windows);
0470                 bridge->dev.parent = parent;
0471                 bridge->sysdata = sys;
0472                 bridge->busnr = sys->busnr;
0473                 bridge->ops = hw->ops;
0474 
0475                 ret = pci_scan_root_bus_bridge(bridge);
0476             }
0477 
0478             if (WARN(ret < 0, "PCI: unable to scan bus!")) {
0479                 pci_free_host_bridge(bridge);
0480                 break;
0481             }
0482 
0483             sys->bus = bridge->bus;
0484 
0485             busnr = sys->bus->busn_res.end + 1;
0486 
0487             list_add(&sys->node, head);
0488         } else {
0489             pci_free_host_bridge(bridge);
0490             if (ret < 0)
0491                 break;
0492         }
0493     }
0494 }
0495 
0496 void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
0497 {
0498     struct pci_sys_data *sys;
0499     LIST_HEAD(head);
0500 
0501     pci_add_flags(PCI_REASSIGN_ALL_BUS);
0502     if (hw->preinit)
0503         hw->preinit();
0504     pcibios_init_hw(parent, hw, &head);
0505     if (hw->postinit)
0506         hw->postinit();
0507 
0508     list_for_each_entry(sys, &head, node) {
0509         struct pci_bus *bus = sys->bus;
0510 
0511         /*
0512          * We insert PCI resources into the iomem_resource and
0513          * ioport_resource trees in either pci_bus_claim_resources()
0514          * or pci_bus_assign_resources().
0515          */
0516         if (pci_has_flag(PCI_PROBE_ONLY)) {
0517             pci_bus_claim_resources(bus);
0518         } else {
0519             struct pci_bus *child;
0520 
0521             pci_bus_size_bridges(bus);
0522             pci_bus_assign_resources(bus);
0523 
0524             list_for_each_entry(child, &bus->children, node)
0525                 pcie_bus_configure_settings(child);
0526         }
0527 
0528         pci_bus_add_devices(bus);
0529     }
0530 }
0531 
0532 #ifndef CONFIG_PCI_HOST_ITE8152
0533 void pcibios_set_master(struct pci_dev *dev)
0534 {
0535     /* No special bus mastering setup handling */
0536 }
0537 #endif
0538 
0539 char * __init pcibios_setup(char *str)
0540 {
0541     if (!strcmp(str, "debug")) {
0542         debug_pci = 1;
0543         return NULL;
0544     }
0545     return str;
0546 }
0547 
0548 /*
0549  * From arch/i386/kernel/pci-i386.c:
0550  *
0551  * We need to avoid collisions with `mirrored' VGA ports
0552  * and other strange ISA hardware, so we always want the
0553  * addresses to be allocated in the 0x000-0x0ff region
0554  * modulo 0x400.
0555  *
0556  * Why? Because some silly external IO cards only decode
0557  * the low 10 bits of the IO address. The 0x00-0xff region
0558  * is reserved for motherboard devices that decode all 16
0559  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
0560  * but we want to try to avoid allocating at 0x2900-0x2bff
0561  * which might be mirrored at 0x0100-0x03ff..
0562  */
0563 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
0564                 resource_size_t size, resource_size_t align)
0565 {
0566     struct pci_dev *dev = data;
0567     resource_size_t start = res->start;
0568     struct pci_host_bridge *host_bridge;
0569 
0570     if (res->flags & IORESOURCE_IO && start & 0x300)
0571         start = (start + 0x3ff) & ~0x3ff;
0572 
0573     start = (start + align - 1) & ~(align - 1);
0574 
0575     host_bridge = pci_find_host_bridge(dev->bus);
0576 
0577     if (host_bridge->align_resource)
0578         return host_bridge->align_resource(dev, res,
0579                 start, size, align);
0580 
0581     return start;
0582 }
0583 
0584 void __init pci_map_io_early(unsigned long pfn)
0585 {
0586     struct map_desc pci_io_desc = {
0587         .virtual    = PCI_IO_VIRT_BASE,
0588         .type       = MT_DEVICE,
0589         .length     = SZ_64K,
0590     };
0591 
0592     pci_io_desc.pfn = pfn;
0593     iotable_init(&pci_io_desc, 1);
0594 }
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