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0011 #ifndef _UAPI__ASM_ARM_PTRACE_H
0012 #define _UAPI__ASM_ARM_PTRACE_H
0013
0014 #include <asm/hwcap.h>
0015
0016 #define PTRACE_GETREGS 12
0017 #define PTRACE_SETREGS 13
0018 #define PTRACE_GETFPREGS 14
0019 #define PTRACE_SETFPREGS 15
0020
0021
0022 #define PTRACE_GETWMMXREGS 18
0023 #define PTRACE_SETWMMXREGS 19
0024
0025 #define PTRACE_OLDSETOPTIONS 21
0026 #define PTRACE_GET_THREAD_AREA 22
0027 #define PTRACE_SET_SYSCALL 23
0028
0029 #define PTRACE_GETCRUNCHREGS 25
0030 #define PTRACE_SETCRUNCHREGS 26
0031 #define PTRACE_GETVFPREGS 27
0032 #define PTRACE_SETVFPREGS 28
0033 #define PTRACE_GETHBPREGS 29
0034 #define PTRACE_SETHBPREGS 30
0035 #define PTRACE_GETFDPIC 31
0036
0037 #define PTRACE_GETFDPIC_EXEC 0
0038 #define PTRACE_GETFDPIC_INTERP 1
0039
0040
0041
0042
0043
0044 #define USR26_MODE 0x00000000
0045 #define FIQ26_MODE 0x00000001
0046 #define IRQ26_MODE 0x00000002
0047 #define SVC26_MODE 0x00000003
0048 #if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
0049
0050
0051
0052
0053 #define USR_MODE 0x00000000
0054 #define SVC_MODE 0x00000000
0055 #else
0056 #define USR_MODE 0x00000010
0057 #define SVC_MODE 0x00000013
0058 #endif
0059 #define FIQ_MODE 0x00000011
0060 #define IRQ_MODE 0x00000012
0061 #define MON_MODE 0x00000016
0062 #define ABT_MODE 0x00000017
0063 #define HYP_MODE 0x0000001a
0064 #define UND_MODE 0x0000001b
0065 #define SYSTEM_MODE 0x0000001f
0066 #define MODE32_BIT 0x00000010
0067 #define MODE_MASK 0x0000001f
0068
0069 #define V4_PSR_T_BIT 0x00000020
0070 #define V7M_PSR_T_BIT 0x01000000
0071 #if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
0072 #define PSR_T_BIT V7M_PSR_T_BIT
0073 #else
0074
0075 #define PSR_T_BIT V4_PSR_T_BIT
0076 #endif
0077
0078 #define PSR_F_BIT 0x00000040
0079 #define PSR_I_BIT 0x00000080
0080 #define PSR_A_BIT 0x00000100
0081 #define PSR_E_BIT 0x00000200
0082 #define PSR_J_BIT 0x01000000
0083 #define PSR_Q_BIT 0x08000000
0084 #define PSR_V_BIT 0x10000000
0085 #define PSR_C_BIT 0x20000000
0086 #define PSR_Z_BIT 0x40000000
0087 #define PSR_N_BIT 0x80000000
0088
0089
0090
0091
0092 #define PSR_f 0xff000000
0093 #define PSR_s 0x00ff0000
0094 #define PSR_x 0x0000ff00
0095 #define PSR_c 0x000000ff
0096
0097
0098
0099
0100 #define APSR_MASK 0xf80f0000
0101 #define PSR_ISET_MASK 0x01000010
0102 #define PSR_IT_MASK 0x0600fc00
0103 #define PSR_ENDIAN_MASK 0x00000200
0104
0105
0106
0107
0108 #ifdef CONFIG_CPU_ENDIAN_BE8
0109 #define PSR_ENDSTATE PSR_E_BIT
0110 #else
0111 #define PSR_ENDSTATE 0
0112 #endif
0113
0114
0115
0116
0117
0118 #define PT_TEXT_ADDR 0x10000
0119 #define PT_DATA_ADDR 0x10004
0120 #define PT_TEXT_END_ADDR 0x10008
0121
0122 #ifndef __ASSEMBLY__
0123
0124
0125
0126
0127
0128
0129 #ifndef __KERNEL__
0130 struct pt_regs {
0131 long uregs[18];
0132 };
0133 #endif
0134
0135 #define ARM_cpsr uregs[16]
0136 #define ARM_pc uregs[15]
0137 #define ARM_lr uregs[14]
0138 #define ARM_sp uregs[13]
0139 #define ARM_ip uregs[12]
0140 #define ARM_fp uregs[11]
0141 #define ARM_r10 uregs[10]
0142 #define ARM_r9 uregs[9]
0143 #define ARM_r8 uregs[8]
0144 #define ARM_r7 uregs[7]
0145 #define ARM_r6 uregs[6]
0146 #define ARM_r5 uregs[5]
0147 #define ARM_r4 uregs[4]
0148 #define ARM_r3 uregs[3]
0149 #define ARM_r2 uregs[2]
0150 #define ARM_r1 uregs[1]
0151 #define ARM_r0 uregs[0]
0152 #define ARM_ORIG_r0 uregs[17]
0153
0154
0155
0156
0157
0158 #define ARM_VFPREGS_SIZE ( 32 * 8 + 4 )
0159
0160
0161 #endif
0162
0163 #endif