include/debug/zynq.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Debugging macro include header
0004  *
0005  *  Copyright (C) 2011 Xilinx
0006  */
0007 #define UART_CR_OFFSET      0x00  /* Control Register [8:0] */
0008 #define UART_SR_OFFSET      0x2C  /* Channel Status [11:0] */
0009 #define UART_FIFO_OFFSET    0x30  /* FIFO [15:0] or [7:0] */
0010
0011 #define UART_SR_TXFULL      0x00000010  /* TX FIFO full */
0012 #define UART_SR_TXEMPTY     0x00000008  /* TX FIFO empty */
0013
0014 #define UART0_PHYS      0xE0000000
0015 #define UART0_VIRT      0xF0800000
0016 #define UART1_PHYS      0xE0001000
0017 #define UART1_VIRT      0xF0801000
0018
0019 #if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
0020 # define LL_UART_PADDR      UART1_PHYS
0021 # define LL_UART_VADDR      UART1_VIRT
0022 #else
0023 # define LL_UART_PADDR      UART0_PHYS
0024 # define LL_UART_VADDR      UART0_VIRT
0025 #endif
0026
0027         .macro  addruart, rp, rv, tmp
0028         ldr \rp, =LL_UART_PADDR @ physical
0029         ldr \rv, =LL_UART_VADDR @ virtual
0030         .endm
0031
0032         .macro  senduart,rd,rx
0033         strb    \rd, [\rx, #UART_FIFO_OFFSET]   @ TXDATA
0034         .endm
0035
0036         .macro  waituartcts,rd,rx
0037         .endm
0038
0039         .macro  waituarttxrdy,rd,rx
0040 1001:       ldr \rd, [\rx, #UART_SR_OFFSET]
0041 ARM_BE8(    rev \rd, \rd )
0042         tst \rd, #UART_SR_TXEMPTY
0043         beq 1001b
0044         .endm
0045
0046         .macro  busyuart,rd,rx
0047 1002:       ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
0048 ARM_BE8(    rev \rd, \rd )
0049         tst \rd, #UART_SR_TXFULL        @
0050         bne 1002b           @ wait if FIFO is full
0051         .endm