include/debug/vf.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2013 Freescale Semiconductor, Inc.
0004  */
0005
0006 #define VF_UART0_BASE_ADDR  0x40027000
0007 #define VF_UART1_BASE_ADDR  0x40028000
0008 #define VF_UART2_BASE_ADDR  0x40029000
0009 #define VF_UART3_BASE_ADDR  0x4002a000
0010 #define VF_UART_BASE_ADDR(n)    VF_UART##n##_BASE_ADDR
0011 #define VF_UART_BASE(n)     VF_UART_BASE_ADDR(n)
0012 #define VF_UART_PHYSICAL_BASE   VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT)
0013
0014 #define VF_UART_VIRTUAL_BASE    0xfe000000
0015
0016     .macro  addruart, rp, rv, tmp
0017     ldr \rp, =VF_UART_PHYSICAL_BASE     @ physical
0018     and \rv, \rp, #0xffffff     @ offset within 16MB section
0019     add \rv, \rv, #VF_UART_VIRTUAL_BASE
0020     .endm
0021
0022     .macro  senduart, rd, rx
0023     strb    \rd, [\rx, #0x7]    @ Data Register
0024     .endm
0025
0026     .macro  busyuart, rd, rx
0027 1001:   ldrb    \rd, [\rx, #0x4]    @ Status Register 1
0028     tst \rd, #1 << 6        @ TC
0029     beq 1001b           @ wait until transmit done
0030     .endm
0031
0032     .macro  waituartcts,rd,rx
0033     .endm
0034
0035     .macro  waituarttxrdy,rd,rx
0036     .endm