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0010 #define DEBUG_LL_PHYS_BASE 0x10000000
0011 #define DEBUG_LL_UART_OFFSET 0x00009000
0012
0013 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
0014 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000
0015
0016 #define DEBUG_LL_UART_PHYS_CRX 0xb0090000
0017
0018 #define DEBUG_LL_VIRT_BASE 0xf8000000
0019
0020 #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
0021
0022 .macro addruart,rp,rv,tmp
0023 .arch armv7-a
0024
0025 @ Make an educated guess regarding the memory map:
0026 @ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
0027 @ should use UART at 0x10009000
0028 @ - all other (RS1 complaint) tiles use UART mapped
0029 @ at 0x1c090000
0030 mrc p15, 0, \rp, c0, c0, 0
0031 movw \rv, #0xc091
0032 movt \rv, #0x410f
0033 cmp \rp, \rv
0034
0035 @ Original memory map
0036 moveq \rp, #DEBUG_LL_UART_OFFSET
0037 orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
0038 orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
0039
0040 @ RS1 memory map
0041 movne \rp, #DEBUG_LL_UART_OFFSET_RS1
0042 orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
0043 orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
0044
0045 .endm
0046
0047 #include <debug/pl01x.S>
0048 #endif