include/debug/sa1100.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* arch/arm/include/debug/sa1100.S
0003  *
0004  * Debugging macro include header
0005  *
0006  *  Copyright (C) 1994-1999 Russell King
0007  *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
0008 */
0009
0010 #define UTCR3       0x0c
0011 #define UTDR        0x14
0012 #define UTSR1       0x20
0013 #define UTCR3_TXE   0x00000002  /* Transmit Enable                 */
0014 #define UTSR1_TBY   0x00000001  /* Transmitter BusY (read)         */
0015 #define UTSR1_TNF   0x00000004  /* Transmit FIFO Not Full (read)   */
0016
0017         .macro  addruart, rp, rv, tmp
0018         mrc p15, 0, \rp, c1, c0
0019         tst \rp, #1         @ MMU enabled?
0020         moveq   \rp, #0x80000000    @ physical base address
0021         movne   \rp, #0xf8000000    @ virtual address
0022
0023         @ We probe for the active serial port here, coherently with
0024         @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
0025         @ We assume r1 can be clobbered.
0026
0027         @ see if Ser3 is active
0028         add \rp, \rp, #0x00050000
0029         ldr \rv, [\rp, #UTCR3]
0030         tst \rv, #UTCR3_TXE
0031
0032         @ if Ser3 is inactive, then try Ser1
0033         addeq   \rp, \rp, #(0x00010000 - 0x00050000)
0034         ldreq   \rv, [\rp, #UTCR3]
0035         tsteq   \rv, #UTCR3_TXE
0036
0037         @ if Ser1 is inactive, then try Ser2
0038         addeq   \rp, \rp, #(0x00030000 - 0x00010000)
0039         ldreq   \rv, [\rp, #UTCR3]
0040         tsteq   \rv, #UTCR3_TXE
0041
0042         @ clear top bits, and generate both phys and virt addresses
0043         lsl \rp, \rp, #8
0044         lsr \rp, \rp, #8
0045         orr \rv, \rp, #0xf8000000   @ virtual
0046         orr \rp, \rp, #0x80000000   @ physical
0047
0048         .endm
0049
0050         .macro  senduart,rd,rx
0051         str \rd, [\rx, #UTDR]
0052         .endm
0053
0054         .macro  waituartcts,rd,rx
0055         .endm
0056
0057         .macro  waituarttxrdy,rd,rx
0058 1001:       ldr \rd, [\rx, #UTSR1]
0059         tst \rd, #UTSR1_TNF
0060         beq 1001b
0061         .endm
0062
0063         .macro  busyuart,rd,rx
0064 1001:       ldr \rd, [\rx, #UTSR1]
0065         tst \rd, #UTSR1_TBY
0066         bne 1001b
0067         .endm