include/debug/renesas-scif.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Renesas SCIF(A) debugging macro include header
0004  *
0005  * Based on r8a7790.S
0006  *
0007  * Copyright (C) 2012-2013 Renesas Electronics Corporation
0008  * Copyright (C) 1994-1999 Russell King
0009  */
0010
0011 #define SCIF_PHYS   CONFIG_DEBUG_UART_PHYS
0012 #define SCIF_VIRT   ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
0013
0014 #if defined(CONFIG_DEBUG_R7S9210_SCIF2) || defined(CONFIG_DEBUG_R7S9210_SCIF4)
0015 /* RZ/A2 SCIFA */
0016 #define FTDR        0x06
0017 #define FSR     0x08
0018 #elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
0019 /* SCIFA */
0020 #define FTDR        0x20
0021 #define FSR     0x14
0022 #else
0023 /* SCIF */
0024 #define FTDR        0x0c
0025 #define FSR     0x10
0026 #endif
0027
0028 #define TDFE    (1 << 5)
0029 #define TEND    (1 << 6)
0030
0031     .macro  addruart, rp, rv, tmp
0032     ldr \rp, =SCIF_PHYS
0033     ldr \rv, =SCIF_VIRT
0034     .endm
0035
0036     .macro  waituartcts,rd,rx
0037     .endm
0038
0039     .macro  waituarttxrdy, rd, rx
0040 1001:   ldrh    \rd, [\rx, #FSR]
0041     tst \rd, #TDFE
0042     beq 1001b
0043     .endm
0044
0045     .macro  senduart, rd, rx
0046     strb    \rd, [\rx, #FTDR]
0047     ldrh    \rd, [\rx, #FSR]
0048     bic \rd, \rd, #TEND
0049     strh    \rd, [\rx, #FSR]
0050     .endm
0051
0052     .macro  busyuart, rd, rx
0053 1001:   ldrh    \rd, [\rx, #FSR]
0054     tst \rd, #TEND
0055     beq 1001b
0056     .endm